Semiconductor device and semiconductor device operating method

Patent metadata

Field	Value
Publication number	US-9306593-B2
Application number	US-201414267790-A
Country	US
Kind code	B2
Filing date	May 1, 2014
Priority date	May 30, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A semiconductor device includes an analog-digital converter circuit. The analog-digital converter circuit includes a delay cell array and an encoder. The delay cell array contains n number of serially-coupled delay cells, receives a reference clock signal, and utilizes an analog input signal as the power supply voltage for the delay cells in each stage. The encoder encodes an output signal from the delay cell in each stage for the delay cell array and outputs the encoded output signal as a digital output signal. The n number of delay cells includes delay quantities weighted for each delay cell. The encoder encodes the output signal of the delay cells in each stage for the delay cell array by weighting corresponding to the number of delay cell stage.

First claim

What is claimed is:

1. A semiconductor device comprising:
an analog-digital converter circuit,
wherein the analog-digital converter circuit includes:
a delay cell array that includes n-number (n is a natural number of 2 or more) of serially-coupled delay cells, receives a reference clock signal, and utilizes an analog input signal as the power supply voltage for delay cells in each stage; and
an encoder that encodes the output signal of the delay cells in each stage of the de…

Assignees

• Renesas Electronics Corp

Inventors

• Kawano Takahiro

Classifications

• H03M1/502 Primary

  Electricity · mapped topic