Analog-digital conversion system and method for controlling the same

Patent metadata

Field	Value
Publication number	US-9306589-B1
Application number	US-201414503585-A
Country	US
Kind code	B1
Filing date	Oct 1, 2014
Priority date	Oct 1, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

An analog-digital conversion system includes an analog-digital converter; and a preamplifier circuit which is provided in the previous stage of the analog-digital converter and differentially amplifies an input analog signal. In the preamplifier circuit, an offset voltage and/or a noise occurs and/or is mixed. The preamplifier circuit outputs two types of analog amplified differential signals where a phase is inverted only with respect to the offset voltage and/or the noise. The analog-digital converter has an averaging circuit which averages the two types of analog amplified differential signals for each clock cycle of sampling preceding an analog-digital conversion and outputs a digital signal based on the differential signal averaged by the averaging circuit.

First claim

What is claimed is:

1. A system, comprising:
a preamplifier circuit configured to differentially amplify an input analog signal and output first and second analog differential signals;
an analog-to-digital converter coupled to the output of the preamplifier circuit; and
an averaging circuit configured to average the first and second analog differential signals,
wherein the preamplifier is configured to mix an offset voltage, and
wherein the preamplifier circuit is configured to output the first and second analog differential signals such that the phase of the first and second analog differential signals is inverted with respect to the offset voltage.

2. A system, comprising:
a preamplifier circuit configured to differentially amplify an input analog signal and output first and second analog differential signals;
an analog-to-digital converter coupled to the output of the preamplifier circuit; and
an averaging circuit configured to average the first and second analog differential signals,
wherein the analog to digital converter is configured to output a digital signal based on the differential signal averaged by the averaging circuit.

3. The system of claim 2 , wherein the averaging circuit further comprises capacitors corresponding to the first and second analog differential signals.

4. The system of claim 3 , wherein the averaging circuit is configured to average the first and second analog differential signals using the capacitors by sampling the capacitors at least once for each clock cycle of a clock.

5. The system of claim 2 , further comprising:
an inverting input terminal;
a non-inverting input terminal; and
an input switching section configured to switch one or more input voltage signals between the inverting input terminal and the non-inverting input terminal.

6. The system of claim 5 , wherein the preamplifier circuit comprises an output switching section configured to switch between the first and second analog differential signals.

7. The system of claim 6 , wherein the averaging circuit includes a distribution section configured to selectively distribute the first and second analog differential signals to first and second capacitors corresponding to the first and second analog signals, respectively.

8. The system of claim 7 , wherein the input switching section, the output switching section, and the distribution section are mutually linked.

9. A method, comprising:
generating first and second analog differential signals by differentially amplifying an input analog signal using a preamplifier circuit;
averaging the first and second analog differential signals; and
outputting a digital signal based on the averaged differential signal; and
mixing an offset voltage using the preamplifier circuit,
wherein generating the first and second analog differential signals further comprises generating the first and second analog differential signals such that the phase of the first and second analog differential signals is inverted with respect to the offset voltage.

10. The method of claim 9 , further comprising switching the input voltage signal between an inverting input terminal and a non-inverting input terminal.

11. The method of claim 10 , further comprising switching the output of the preamplifier circuit between the first and second analog differential signals.

12. The method of claim 11 , further comprising:
Distributing the first and second analog differential signals to first and second capacitors corresponding to the first and second analog differential signals, respectively.

13. The method of claim 12 , wherein switching the input voltage signal, switching the output of the preamplifier, and distributing the first and second analog differential signals are performed using mutually linked switches.

14. The method of claim 9 , further comprising sampling the first and second analog differential signals using first and second capacitors corresponding to the first and second analog differential signal, respectively.

15. The method of claim 14 , further wherein the first and second analog differential signals are sampled using the first and second capacitors a plurality of times for each clock cycled of a clock.

16. The method of claim 9 , wherein averaging the first and second analog differential signals comprises linearly combining the electrical charges of the first and second analog differential signals.

Assignees

• Spansion Llc
• Cypress Semicondcutor Corp

Inventors

• Okura Tetsuro
• Ito Yusaku
• Sadamatsu Hirohiko

Classifications

• H03M1/0609 Primary

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error · CPC title

• H03M1/442

  using switched capacitors · CPC title

• H03F1/08

  Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements (wide-band amplifiers with inter-stage coupling networks incorporating these impedances H03F1/42) · CPC title

• H03M1/0626

  by filtering · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title