Delay locked loop, method of operating the same, and memory system including the same

Patent metadata

Field	Value
Publication number	US-9306583-B2
Application number	US-201514638363-A
Country	US
Kind code	B2
Filing date	Mar 4, 2015
Priority date	Mar 4, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit.

First claim

What is claimed is:

1. A delay locked loop comprising:
a delay line configured to output an output clock by delaying an input clock by a first time on the basis of a select value;
a phase detector configured to detect a phase of the output clock;
a delay line control unit configured to determine the select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value, wherein n is a positive integer; and…

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Soon Suk
• Cho Youngjin
• Han Kyuwook
• Park Jaegeun

Classifications

• G11C7/22

  Physics · mapped topic

• H03L7/085

  Electricity · mapped topic

• H03L7/0802 Primary

  Electricity · mapped topic

• H03L7/0814 Primary

  Electricity · mapped topic

• Y02D10/00

  Cross-Sectional Technologies · mapped topic