Method and circuit for controlled gain reduction of a gain stage

Patent metadata

Field	Value
Publication number	US-9306522-B2
Application number	US-201414191634-A
Country	US
Kind code	B2
Filing date	Feb 27, 2014
Priority date	Jul 10, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. A multi-stage amplifier is described. The multi-stage amplifier comprises a first amplification stage configured to provide a stage output voltage at a stage output node. Furthermore, the amplifier comprises an intermediate amplification stage comprising an amplifier current source configured to provide an amplifier current and an amplifier transistor arranged in series with the amplifier current source. A gate of the amplifier transistor is coupled to the stage output node of the first amplification stage. The intermediate amplification stage is configured to provide an amplified or attenuated stage output voltage at a midpoint between the amplifier current source and the amplifier transistor.

First claim

What is claimed is:

1. A multi-stage amplifier comprising
a first amplification stage configured to provide a stage output voltage at a stage output node;
an intermediate amplification stage comprising
an amplifier current source configured to provide an amplifier current; and
an amplifier transistor arranged in series with the amplifier current source; wherein a gate of the amplifier transistor is coupled to the stage output node of the first amplification stage; wherein the intermediate amplification stage is configured, to provide an amplified or attenuated stage output voltage at a midpoint between the amplifier current source and the amplifier transistor; and

a gain control circuit configured to reduce an effective output impedance of the amplifier transistor by providing a current feedback to the midpoint;

wherein
the gain control circuit comprises a control transistor;
a gate of the control transistor is coupled to the stage output node of the first amplification stage;
an input port of the control transistor is coupled to an input port of the amplifier transistor;
the gain control circuit comprises current mapping means configured to map a current at an output port of the control transistor to the midpoint; and
an output port of the amplifier transistor is coupled to the midpoint.

2. The multi-stage amplifier of claim 1 , wherein the control transistor is a metal oxide semiconductor field effect transistor of a same type as the amplifier transistor.

3. The multi-stage amplifier of claim 2 , wherein the diode transistor and the mirror transistor are P-type metal oxide semiconductor field effect transistors.

4. The multi-stage amplifier of claim 2 , wherein
a gate of the diode transistor is coupled with a gate of the mirror transistor;
an input port of the diode transistor and an input port of the mirror transistor are coupled with a supply voltage; and
the amplifier current source is coupled with the supply voltage.

5. The multi-stage amplifier of claims 2 , wherein
an output port of the diode transistor is coupled with an output port of the control transistor; and
an output port of the mirror transistor is coupled to the midpoint.

6. The multi-stage amplifier of claim 1 , wherein the current mapping means comprise a current mirror comprising a diode transistor and a mirror transistor.

7. The multi-stage amplifier of claim 1 , wherein the gain control circuit is configured to reduce the effective output impedance of the amplifier transistor by a factor (1−N), with 0<N<1, wherein N is a rational number.

8. The multi-stage amplifier of claim 1 , wherein the amplifier transistor is an N-type metal oxide semiconductor field effect transistor.

9. The multi-stage amplifier of claim 1 , wherein the amplifier current is constant.

10. The multi-stage amplifier of claim 1 , wherein the first amplification stage comprises a differential amplification stage configured to provide the stage output voltage at the stage output node, based on a first input voltage at a first stage input node and a second input voltage at a second stage input node.

11. The multi-stage amplifier of claim 1 , further comprising
an output amplification stage configured to provide a load current at an amplifier output voltage to a load; wherein an input of the output amplification stage is coupled to an output of the second amplification stage; and
voltage sensing means configured to provide an indication of the amplifier output voltage; wherein the indication of the amplifier output voltage is fed back to an input of the first amplification stage.

12. A method for stabilizing a multi-stage amplifier, the method comprising
providing a stage output voltage at a stage output node of a first amplification stage;
providing, by an amplifier current source, an amplifier current through an amplifier transistor within an intermediate amplification stage; wherein a gate of the amplifier transistor is coupled to the stage output node of the first amplification stage; wherein the intermediate amplification stage provides an amplified or attenuated stage output voltage at a midpoint between the amplifier current source and the amplifier transistor;
reducing an effective output impedance of the amplifier transistor by providing, by a gain control circuit, a current feedback to the midpoint and wherein
the gain control circuit comprises a control transistor;
a gate of the control transistor is coupled to the stage output node of the first amplification stage;
an input port of the control transistor is coupled to an input port of the amplifier transistor; and
an output port of the amplifier transistor is coupled to the midpoint,
the method further comprising mapping, by the gain control circuit, a current at an output port of the control transistor to the midpoint.

13. The method of claim 12 wherein said first amplification stage comprises a differential pair.

14. The method of claim 12 wherein said differential pair comprises MOSFETs.

Assignees

• Dialog Semiconductor Gmbh

Inventors

• Kronmueller Frank

Classifications

• H03F1/342

  in field-effect transistor amplifiers · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03G3/30 Primary

  in amplifiers having semiconductor devices · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title