Integrated circuit and method of manufacturing an integrated circuit

Patent metadata

Field	Value
Publication number	US-9306058-B2
Application number	US-201314043971-A
Country	US
Kind code	B2
Filing date	Oct 2, 2013
Priority date	Oct 2, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

An integrated circuit includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device comprising forming a transistor in a semiconductor substrate having a main surface, wherein forming the transistor comprises:
forming a source region;
forming a drain region;
forming a channel region;
forming a drift zone;
forming a gate electrode adjacent to the channel region, wherein forming the gate electrode comprises forming a gate trench in the main surface of the semiconductor substrate; and…

Assignees

• Infineon Technologies Ag

Inventors

• Vielemeyer Martin
• Meiser Andreas
• Schloesser Till
• Hirler Franz
• Poelzl Martin

Classifications

• H10P30/222

  Electricity · mapped topic

• H10P30/208

  Electricity · mapped topic

• H10P30/204

  Electricity · mapped topic

• H10D64/01348

  Electricity · mapped topic

• H10D64/519

  Electricity · mapped topic