Semiconductor device with trench-like feed-throughs

Patent metadata

Field	Value
Publication number	US-9306056-B2
Application number	US-61014809-A
Country	US
Kind code	B2
Filing date	Oct 30, 2009
Priority date	Oct 30, 2009
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

First claim

What is claimed is:

1. A semiconductor device comprising:
an electrically conductive substrate layer;
a drain contact, wherein said substrate layer is separated from said drain contact by an intervening layer;
a plurality of gate trenches that extend into but not completely through said intervening layer, each of said gate trenches filled with a first filler material;
a plurality of source contact trenches that extend into but not completely through said intervening layer, each of said source contact trenches filled with a second filler material different from said first filler material, wherein said source contact trenches are interleaved between said gate trenches; and
a plurality of feed-through trenches that extend completely through said intervening layer to said substrate layer, each of said feed-through trenches filled with said second filler material and coupled to said drain contact, wherein said feed-through trenches are adjacent to each other under said drain contact and are not interleaved with said gate trenches and are not interleaved with said source contact trenches.

2. The semiconductor device of claim 1 wherein said first filler material comprises polysilicon and said second filler material comprises tungsten.

3. The semiconductor device of claim 1 wherein said feed-through trenches are each lined with a conformal coating that separates said second filler material from said intervening layer.

4. The semiconductor device of claim 3 wherein said conformal coating comprises material selected from the group consisting of: titanium and titanium-nitride.

5. The semiconductor device of claim 3 wherein said conformal coating comprises a thickness of titanium of about 600 Angstroms and a thickness of titanium-nitride of about 200 Angstroms.

6. The semiconductor device of claim 1 wherein said device comprises a flip chip having a plurality of solder balls formed on a surface thereof, wherein said drain contact is coupled to at least one of said solder balls.

7. The semiconductor device of claim 1 wherein said feed-through trenches are non-uniformly distributed under said drain contact between said drain contact and said substrate layer, wherein said feed-through trenches are concentrated toward a source region of said device.

8. The semiconductor device of claim 1 wherein each trench in said plurality of feed-through trenches has a depth of approximately 8.7 microns at their shallowest points, a width of approximately 0.9 microns, and a pitch of approximately 1.7 microns.

9. The semiconductor device of claim 1 wherein said feed-through trenches are non-uniformly distributed under a solder ball coupled to said drain contact.

10. A flip chip semiconductor device comprising:
a plurality of solder balls comprising a solder ball coupled to a drain contact on a first surface of said device;
a first metal layer on a second surface of said device, said second surface opposite said first surface;
a substrate layer adjacent said first metal layer, wherein said substrate layer is separated from said drain contact by an intervening layer;
a plurality of gate trenches that extend into but not completely through said intervening layer, each of said gate trenches filled with a first filler material;
a plurality of source contact trenches that extend into but not completely through said intervening layer, each of said source contact trenches filled with a second filler material different from said first filler material, wherein said source contact trenches are interleaved between said gate trenches, and wherein said source contact trenches are in contact with a second metal layer but said gate trenches are isolated from said second metal layer; and
a plurality of feed-through trenches that extend completely through said intervening layer to said substrate layer, each of said feed-through trenches with said second filler material and coupled to said drain contact, wherein said feed-through trenches pass through said intervening layer and into said substrate layer, wherein said feed-through trenches are adjacent to each other under said drain contact and are not interleaved with said gate trenches and are not interleaved with said source contact trenches, and further wherein in operation said device comprises a circuit from a source contact through said intervening layer, said substrate layer, and said feed-through trenches to said drain contact.

11. The semiconductor device of claim 10 wherein said first filler material comprises polysilicon and said second filler material comprises tungsten.

12. The semiconductor device of claim 10 wherein said source contact trenches and said feed-through trenches are each lined with a conformal coating that separates said second filler material from said intervening layer.

13. The semiconductor device of claim 12 wherein said conformal coating comprises material selected from the group consisting of: titanium and titanium-nitride.

14. The semiconductor device of claim 10 wherein said feed-through trenches are non-uniformly distributed under said drain contact between said drain contact and said substrate layer, wherein a greater concentration of said feed-through trenches is located toward said source contact.

15. The semiconductor device of claim 10 wherein said feed-through trenches are non-uniformly distributed under said solder ball.

16. A method of fabricating a flip chip, said method comprising:
forming a plurality of gate trenches in a surface of an epitaxial layer of a structure, said gate trenches extending partially into but not completely through said epitaxial layer, wherein a first plurality of source contact trenches are also formed in said surface of said epitaxial layer, said source gate trenches extending partially into but not completely through said epitaxial layer, said source contact trenches interleaved between said gate trenches;
forming a plurality of feed-through trenches in said surface, said feed-through trenches extending completely through said epitaxial layer and into a substrate layer adjoining a second surface of said epitaxial layer; and
depositing a first filler material into said source contact trenches and depositing a second filler material into both said gate trenches and said feed-through trenches, said second filler material different from said first filler material, wherein said gate trenches are subsequently electrically coupled to a first solder ball used as a source contact, wherein said feed-through trenches are adjacent to each other under a drain contact and are not interleaved with said gate trenches and are not interleaved with said source contact trenches, and wherein said feed-through trenches are subsequently electrically coupled to a second solder ball used as a drain contact.

17. The method of claim 16 wherein said first filler material comprises polysilicon and said second filler material comprises tungsten.

18. The method of claim 16 further comprising, in a same process step performed after said gate trenches and said feed-through trenches are formed and before said second filler material is deposited, depositing a conformal coating that lines said gate trenches and that lines said feed-through trenches.

19. The method of claim 18 wherein said conformal coating comprises material selected from the group consisting of: titanium and titanium-nitride.

20. The method of claim 16 wherein said feed-through trenches are non-uniformly distributed within said drain region under said drain contact, wherein said feed-through

Assignees

• Pattanayak Deva
• Owyang King
• Kasem Mohammed
• Terrill Kyle
• Katraro Reuven
• Chen Kuo-In
• Choi Calvin
• Chen Qufei
• Wong Ronald
• Lui Kam Hong
• Xu Robert
• Vishay Siliconix

Inventors

• Pattanayak Deva
• Owyang King
• Kasem Mohammed
• Terrill Kyle
• Katraro Reuven
• Chen Kuo-In
• Choi Calvin
• Chen Qufei
• Wong Ronald
• Lui Kam Hong
• Xu Robert

Classifications

• H10W72/936

  Multiple bond pads having different shapes · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/251

  Materials · CPC title

• H10W72/242

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/232

  Plan-view shape, i.e. in top view · CPC title