Electronic device including graphene

Patent metadata

Field	Value
Publication number	US-9306005-B2
Application number	US-201314103079-A
Country	US
Kind code	B2
Filing date	Dec 11, 2013
Priority date	Dec 11, 2012
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 10 19 cm −3 , and a depletion width of less than or equal to 3 nm.

First claim

What is claimed is:

1. An electronic device comprising:
a semiconductor layer including an area, wherein
the area includes
a depletion width of less than or equal to 3 nm;

a graphene directly contacting the area of the semiconductor layer; and
a metal layer on the graphene.

2. The electronic device of claim 1 ,
wherein the semiconductor layer includes a constant doping density in overall;
or the area includes a doping density that is less than or equal to 10 19 cm −3 .

3. The electronic device of claim 1 , wherein the semiconductor layer is a semiconductor substrate.

4. The electronic device of claim 1 , wherein the semiconductor layer includes at least one of silicon, germanium, silicon-germanium, a II-VI group semiconductor, and a group semiconductor.

5. The electronic device of claim 4 , wherein the semiconductor layer is weakly doped.

6. An electronic device, comprising:
a semiconductor layer including an area,
the area of the semiconductor layer including one of a depletion width of less than or equal to 3 nm and a constant doping density in overall;

a metal layer connected to the area of the semiconductor layer; and
a graphene between the metal layer and the area of the semiconductor layer,
the graphene directly contacting the area of the semiconductor layer,
the graphene is configured to reduce an energy barrier between the metal layer and the area of the semiconductor layer.

7. A field effect transistor (FET) comprising:
the electronic device of claim 6 ;
first and second graphenes separated from each other;
source and drain electrodes; and
a gate electrode, wherein
the semiconductor layer of the electronic device includes a channel area, a source area, and a drain area,
the area of the semiconductor layer is one of the source area and the drain area,
the source and drain areas are separated from each other,
the first and second graphenes directly contact the source and drain areas of the semiconductor layer, respectively,
the source and drain electrodes are on the first and second graphenes, respectively, and
the gate electrode faces the channel area.

8. The FET of claim 7 , wherein a doping density in the source and drain areas is one of:
equal to the doping density in the channel area, and
less than or equal to 10 19 cm −3 .

9. The FET of claim 7 , further comprising:
a gate insulation layer between the channel area and the gate electrode.

10. The FET of claim 7 , wherein the semiconductor layer is a semiconductor substrate.

11. The FET of claim 10 , wherein the semiconductor layer includes at least one of silicon, germanium, silicon-germanium, a II-VI group semiconductor, and a III-V group semiconductor.

12. The FET of claim 7 , wherein the depletion width of the source area and the drain area in the semiconductor layer is less than or equal to 3 nm.

13. The FET of claim 7 , wherein the semiconductor layer is a semiconductor substrate, and at least one part of the semiconductor substrate below the first and second graphenes includes a depletion width that is less than or equal to 3 nm.

14. The electronic device of claim 6 , wherein the graphene is one of a single layer and two layers.

15. The electronic device of claim 6 , wherein
the graphene does not have a bandgap so a Fermi level between the metal layer and the graphene does not vary, and
the depletion width between the area of the semiconductor layer and the graphene is less than or equal to 3 nm.

16. The electronic device of claim 6 , wherein
the semiconductor layer is a substrate, and
the substrate includes at least one of silicon, germanium, silicon-germanium, a II-VI group semiconductor, and a III-V group semiconductor.

17. The electronic device of claim 6 , further comprising:
a gate insulating layer connected to a portion of the semiconductor layer that is adjacent to the area of the semiconductor layer; and
a gate electrode connected to the gate insulating layer,
wherein the gate insulating layer is between the gate electrode and the portion of the semiconductor layer.

18. The electronic device of claim 6 , wherein
the area of the semiconductor layer is a first area of the semiconductor layer;
the semiconductor layer includes a second area spaced apart from the first area;
the electronic device further includes:
a second metal layer connected to the second area, and
a second graphene between the second metal layer and the second area; and
the second graphene is configured to reduce an energy barrier between the second metal layer and the second area of the semiconductor layer.

19. The electronic device of claim 18 , further comprising:
a gate insulating layer on a portion of the semiconductor layer between the first area and the second area; and
a gate electrode on the gate insulating layer, wherein
the gate insulating layer is between the first graphene and the second graphene.

20. The electronic device of claim 18 , wherein the first graphene and the second graphene are spaced apart from each other on a same surface of the semiconductor layer.

21. The electronic device of claim 18 , wherein the doping density of the first area and the doping density of the second area of the semiconductor layer are the same as a doping density of a portion of the semiconductor layer between the first area and the second area.

22. The electronic device of claim 18 , wherein
the first graphene is one of a single layer and two layers, and
the second graphene is one a single layer and two layers.

23. The electronic device of claim 1 , wherein a width of the graphene is less than a width of the semiconductor layer.

24. The electronic device of claim 6 , wherein a width of the graphene is less than a width of the semiconductor layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Byun Kyung-Eun
• Park Seong-Jun
• Seo David
• Song Hyun-Jae
• Lee Jae-Ho
• Chung Hyun-Jong
• Heo Jin-Seong

Classifications

• H10D12/211

  Gated diodes · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title

• H10D62/378

  Contact regions to the substrate regions · CPC title

• H10D62/882 Primary

  Graphene · CPC title