Semiconductor device

Patent metadata

Field	Value
Publication number	US-9306002-B2
Application number	US-201414314726-A
Country	US
Kind code	B2
Filing date	Jun 25, 2014
Priority date	Jun 26, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer of a first conductivity type; an element isolation well of a second conductivity type, which is formed on a surface of the semiconductor layer and isolates an element formation region; a field insulating film configured to cover a surface of the element isolation well; an interlayer insulating film formed on the semiconductor layer; a wiring formed on the interlayer insulating film; and a conductive film formed on the wiring and the field insulating film, a voltage potential of the conductive film being fixed to be a specified voltage potential.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor layer of a first conductivity type;
an element isolation well of a second conductivity type, which is formed in the semiconductor layer and isolates an element formation region;
a field insulating film configured to cover a surface of the element isolation well;
an interlayer insulating film formed on the field insulating film;
a wiring formed on the interlayer insulating film; and
a conductive film formed on the field insulating film, a voltage potential of the conductive film being fixed to be a specified voltage potential,
wherein the wiring intersects the element isolation well when viewed from the top, and
wherein the conductive film is interposed between the field insulating film and an intersection portion of the wiring.

2. The semiconductor device of claim 1 , wherein the element formation region includes a low voltage element region in which an element operated with a low reference voltage is formed and a high voltage element region in which an element operated with a high reference voltage is formed, the high reference voltage being higher than the low reference voltage, the low and high voltage element regions being isolated by the element isolation well, and
wherein the wiring is electrically connected to the element formed in the high voltage element region.

3. The semiconductor device of claim 1 , wherein in a direction in which the element isolation well intersects the wiring at the intersection portion, a length of the conductive film is equal to or larger than a length of the intersection portion.

4. The semiconductor device of claim 1 , wherein in a direction in which the wiring intersects the element isolation well at the intersection portion, a length of the conductive film is smaller than a length of the intersection portion.

5. The semiconductor device of claim 1 , wherein in a direction in which the wiring intersects the element isolation well at the intersection portion, a length of the conductive film is equal to or larger than a length of the intersection portion.

6. The semiconductor device of claim 1 , wherein the element isolation well is formed in a band shape, and
wherein the conductive film is formed in a band shape along the element isolation well.

7. The semiconductor device of claim 1 , wherein the element isolation well is formed in a band shape that forms a closed curve when viewed from the top, and
wherein the conductive film is formed in a band shape that forms a closed curve along the element isolation well.

8. The semiconductor device of claim 1 , further comprising a MOS transistor formed in the element formation region,
wherein the conductive film includes the same material as a gate of the MOS transistor and formed in the same layer as the gate.

9. The semiconductor device of claim 8 , wherein the gate and the conductive film include polysilicon.

10. The semiconductor device of claim 1 , wherein the interlayer insulating film includes a wiring layer, and
wherein the conductive film is formed by a wiring film disposed in the wiring layer.

11. The semiconductor device of claim 1 , wherein the interlayer insulating film covers a wiring layer,
wherein the conductive film is formed by a wiring film disposed in the wiring layer.

12. The semiconductor device of claim 1 , wherein the interlayer insulating film covers the conductive film.

13. A semiconductor device comprising:
a semiconductor layer of a first conductivity type;
an element isolation well of a second conductivity type, which is formed in the semiconductor layer and isolates an element formation region;
a field insulating film configured to cover a surface of the element isolation well;
an interlayer insulating film formed on the field insulating film;
a wiring formed on the interlayer insulating film; and
a conductive film formed on the field insulating film, a voltage potential of the conductive film being fixed to be a specified voltage potential,
wherein the element formation region includes a low voltage element region in which an element operated with a low reference voltage is formed and a high voltage element region in which an element operated with a high reference voltage is formed, the high reference voltage being higher than the low reference voltage, the low and high voltage element regions being isolated by the element isolation well, and
wherein the wiring is electrically connected to the element formed in the high voltage element region.

14. The semiconductor device of claim 13 , wherein the wiring intersects the element isolation well when viewed from the top, and
wherein the conductive film is interposed between the field insulating film and an intersection portion of the wiring.

15. The semiconductor device of claim 14 , wherein in a direction in which the element isolation well intersects the wiring at the intersection portion, a length of the conductive film is equal to or larger than a length of the intersection portion.

16. The semiconductor device of claim 14 , wherein in a direction in which the wiring intersects the element isolation well at the intersection portion, a length of the conductive film is smaller than a length of the intersection portion.

17. The semiconductor device of claim 14 , wherein in a direction in which the wiring intersects the element isolation well at the intersection portion, a length of the conductive film is equal to or larger than a length of the intersection portion.

18. The semiconductor device of claim 13 , wherein the element isolation well is formed in a band shape, and
wherein the conductive film is formed in a band shape along the element isolation well.

19. The semiconductor device of claim 13 , wherein the element isolation well is formed in a band shape that forms a closed curve when viewed from the top, and
wherein the conductive film is formed in a band shape that forms a closed curve along the element isolation well.

20. The semiconductor device of claim 13 , further comprising a MOS transistor formed in the element formation region,
wherein the conductive film includes the same material as a gate of the MOS transistor and formed in the same layer as the gate.

21. The semiconductor device of claim 20 , wherein the gate and the conductive film include polysilicon.

22. The semiconductor device of claim 13 , wherein the interlayer insulating film includes a wiring layer, and
wherein the conductive film is formed by a wiring film disposed in the wiring layer.

23. The semiconductor device of claim 13 , wherein the interlayer insulating film covers a wiring layer,
wherein the conductive film is formed by a wiring film disposed in the wiring layer.

24. The semiconductor device of claim 13 , wherein the interlayer insulating film covers the conductive film.

Assignees

• Rohm Co Ltd

Inventors

• Fujie Shusaku

Classifications

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D62/157

  Impurity concentrations or distributions · CPC title