Semiconductor device

Patent metadata

Field	Value
Publication number	US-9305996-B2
Application number	US-201414310407-A
Country	US
Kind code	B2
Filing date	Jun 20, 2014
Priority date	Feb 21, 2007
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a first insulating film formed on the semiconductor substrate;
an etching stopper film formed on the first insulating film;
a second insulating film formed on the etching stopper film;
a first plug, that is connected to the semiconductor substrate, formed in the first insulating film, the etching stopper film and the second insulating film;
a capacitor formed on the second insulating film;
a third insulating film formed on the second insulating film and the capacitor; and
a second plug, that is connected to the first plug, formed in the third insulating film,
wherein:
the first plug includes a first part located in the first insulating film and the etching stopper film;
the first plug includes a second part located only in the second insulating film; and
a diameter of the second part is larger than a diameter of the first part.

2. The semiconductor device according to claim 1 , wherein a thickness of the second insulating film is equal to or less than 100 nm.

3. The semiconductor device according to claim 1 , wherein the etching stopper film includes any one of insulating materials selected from a group consisting of silicon oxide nitride, silicon nitride, aluminum oxide, titanium oxide, zirconium oxide, magnesium oxide, and MgTiOx.

4. The semiconductor device according to claim 1 , wherein a thickness of the etching stopper film is between 20 nm and 150 nm both inclusive.

5. The semiconductor device according to claim 1 , further comprising a barrier film formed between the etching stopper film and the capacitor.

6. The semiconductor device according to claim 1 , further comprising a barrier film formed above the capacitor.

7. The semiconductor device according to claim 1 , wherein a thickness of the second part of the first plug is smaller than a thickness of the first part of the first plug.

Assignees

• Fujitsu Semiconductor Ltd

Inventors

• Nagai Kouichi

Classifications

• H10D1/692 Primary

  Electrodes · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title

• H10B53/40

  characterised by the peripheral circuit region · CPC title

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H10B53/30 Primary

  characterised by the memory core region · CPC title