Nonvolatile semiconductor memory device and method of manufacturing the same
US-8952441-B2 · Feb 10, 2015 · US
Nonvolatile semiconductor memory device and method of manufacturing the same
US9305936B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9305936-B2 |
| Application number | US-201514854500-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 15, 2015 |
| Priority date | Jul 3, 2013 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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Abstract
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According to one embodiment, a nonvolatile semiconductor memory device includes a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of a semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is parallel to the surface of the semiconductor substrate, and first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction which is perpendicular to the first and second directions respectively.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a nonvolatile semiconductor memory device including a semiconductor substrate; a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of the semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9305936B2 cover?
- According to one embodiment, a nonvolatile semiconductor memory device includes a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of a semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure ex…
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification H10D30/0411. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).