Semiconductor devices having a silicon-germanium channel layer and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9305928-B2
Application number	US-201414175076-A
Country	US
Kind code	B2
Filing date	Feb 7, 2014
Priority date	Mar 15, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.

First claim

What is claimed is:

1. A method of forming a semiconductor memory device, the method comprising:
forming a silicon-germanium channel layer on a substrate in a peripheral circuit region, wherein the substrate includes a cell array region and the peripheral circuit region;
sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer;
removing the first and second insulating layers from the cell array region;
forming a conductive layer on the substrate in the cell array region and the peripheral circuit region after removing the first and second insulating layers; and
patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region,
wherein sequentially forming the first and second insulating layers comprises forming the first insulating layer at a first temperature and forming the second insulating layer at a second temperature higher than the first temperature.

2. The method of claim 1 , wherein the first temperature is lower than 750° C, and the second temperature is higher than 750° C.

3. The method of claim 1 , wherein the first insulating layer has a first thickness thinner than a second thickness of the second insulating layer.

4. The method of claim 1 , wherein:
the peripheral circuit region includes a first peripheral circuit region and a second peripheral circuit region; and
the method further comprises:
removing the first and second insulating layers from the second peripheral circuit region without removing the first and second insulating layers from the first peripheral circuit region; and
sequentially forming a third insulating layer and a fourth insulating layer on the substrate in the first and second peripheral circuit regions after removing the first and second insulating layers from the second peripheral circuit region without removing the first and second insulating layers from the first peripheral circuit region.

5. The method of claim 4 , wherein sequentially forming the third and fourth insulating layers comprises forming the third insulating layer at a third temperature and forming the fourth insulating layer at a fourth temperature higher than the third temperature.

6. The method of claim 4 , wherein the fourth insulating layer includes a high-k dielectric layer having a dielectric constant greater than a dielectric constant of silicon oxide.

7. The method of claim 4 , wherein the third insulating layer has a third thickness thicker than a fourth thickness of the fourth insulating layer.

8. The method of claim 1 , wherein sequentially forming the first and second insulating layers comprises forming the second insulating layer by increasing a temperature from the first temperature to the second temperature.

9. A method of forming a semiconductor device, the method comprising:
forming a silicon-germanium channel layer on a substrate in a peripheral circuit region, wherein the substrate comprises a cell array region and the peripheral circuit region;
sequentially forming a first insulating layer at a first temperature and a second insulating layer at a second temperature higher than the first temperature on the silicon-germanium channel layer, wherein the first insulating layer contacts the silicon-germanium channel layer;
removing the first and second insulating layers from the cell array region;
forming a conductive layer on the substrate in the cell array region and the peripheral circuit region after removing the first and second insulating layers from the cell array region; and
forming a bit line in the cell array region and a gate electrode in the peripheral circuit region by patterning the conductive layer.

10. The method of claim 9 , wherein the first temperature is lower than 750° C., and the second temperature is higher than 750° C.

11. The method of claim 10 , wherein the first temperature is in a range of about 400° C. to about 700° C.

12. The method of claim 9 , wherein:
the first insulating layer comprises a silicon oxide layer; and
the second insulating layer comprises a high-k dielectric layer having a dielectric constant higher than a dielectric constant of silicon oxide.

13. The method of claim 9 , wherein the first insulating layer has a first thickness thinner than a second thickness of the second insulating layer.

14. The method of claim 9 , wherein the bit line contacts an upper surface of the substrate.

15. The method of claim 14 , further comprising forming a buried word line structure in the cell array region before forming the silicon-germanium channel layer.

16. The method of claim 9 , wherein:
the peripheral circuit region comprises a first peripheral circuit region and a second peripheral circuit region;
the gate electrode comprises a first gate electrode formed in the first peripheral circuit region; and
the method further comprises:
removing the first and second insulating layers from the second peripheral circuit region at least partially concurrently with removing the first and second insulating layers from the cell array region;
sequentially forming a third insulating layer and a fourth insulating layer in the first and second peripheral circuit regions after removing the first and second insulating layers from the second peripheral circuit region and before forming the conductive layer, wherein sequentially forming the third and fourth insulating layers comprises forming the third insulating layer at a third temperature and forming the fourth insulating layer at a fourth temperature higher than the third temperature; and
forming a second gate electrode in the second peripheral circuit region by patterning the conductive layer.

17. The method of claim 16 , wherein the third temperature is lower than 750° C., and the fourth temperature is higher than 750° C.

18. The method of claim 17 , wherein the third insulating layer has a third thickness thicker than a fourth thickness of the fourth insulating layer.

19. A method of forming a semiconductor device, the method comprising:
forming a silicon-germanium channel layer on a substrate in a first peripheral circuit region and a second peripheral circuit region, wherein the substrate comprises a cell array region and the first and second peripheral circuit regions;
sequentially forming a first insulating layer at a first temperature and a second insulating layer at a second temperature higher than the first temperature on the silicon-germanium channel layer, wherein the first insulating layer contacts the silicon-germanium channel layer;
removing the first and second insulating layers from the cell array region and the second peripheral circuit region without removing the first and second insulating layers from the first peripheral circuit region;
sequentially forming a third insulating layer and a fourth insulating layer on the silicon-germanium channel layer after removing the first and second insulating layers from the cell array region and the second peripheral circuit region without removing the first and second insulating layers from the first peripheral circuit region, wherein sequentially forming the third and fourth insulating layers comprises forming the third insulating layer at a third temperature and forming the fourth insulating layer at a fourth temperature higher than the third temperature, and the third insulating layer formed in the second peripheral circuit region contacts the silicon-germanium channel layer;
forming a conductive layer on the substrate in the cell array

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Youngkuk
• An Ho-Kyun
• Yeo Jaehyun
• Im Badro
• Lim Hanjin
• Jang Sungho
• Jeon Insang

Classifications

• H10D84/0128 Primary

  Manufacturing their channels · CPC title

• H10D84/0144 Primary

  Manufacturing their gate insulating layers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H01L27/10861

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic