Semiconductor integrated circuit device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9305925-B2
Application number	US-201414531336-A
Country	US
Kind code	B2
Filing date	Nov 3, 2014
Priority date	Nov 26, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

In order to achieve high-speed operation of an eDRAM, the eDRAM includes: a selection MISFET having a gate electrode that serves as a word line, a source region, and a drain region; a source plug electrode coupled to the source region; and a drain plug electrode coupled to the drain region DR 1 . The eDRAM further includes: a capacitive plug electrode coupled to the drain plug electrode; a bit line coupled to the source plug electrode; a stopper film covering the bit line; and a capacitive element that is formed over the stopper film and has a first electrode, a dielectric film, and a second electrode. The first electrode is coupled to the capacitive plug electrode, and the height of the capacitive plug electrode and that of the bit line are equal to each other.

First claim

What is claimed is:

1. A semiconductor integrated circuit device comprising:
a semiconductor substrate;
a word line extending in a first direction in a main surface of the semiconductor substrate;
a bit line extending in a second direction that intersects with the first direction in the main surface of the semiconductor substrate;
a gate electrode that is formed in the main surface of the semiconductor substrate and serves as the word line;
a MISFET having a source region…

Assignees

• Renesas Electronics Corp

Inventors

• Namioka Seigo

Classifications

• H10W20/089

  Electricity · mapped topic

• H10W20/076

  Electricity · mapped topic

• H10W20/40

  Electricity · mapped topic

• H10W20/071

  Electricity · mapped topic

• H10W20/062

  Electricity · mapped topic