Non-circular die package interconnect

Patent metadata

Field	Value
Publication number	US-9305901-B2
Application number	US-201414334390-A
Country	US
Kind code	B2
Filing date	Jul 17, 2014
Priority date	Jul 17, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A computing component may consist of a die package that has at least a board, first computing layer, and second computing layer. Dielectric layers can separate each of the board, first computing layer, and second computing layer. The first computing layer may be disposed between the board and second computing layer. One or more interconnects can continuously extend from the second computing layer to the board with a non-circular cross-section shape.

First claim

What is claimed is:

1. An apparatus comprising:
a die package comprising a board, first die layer, and second die layer each separated by a dielectric layer, the first die layer disposed between the board and second die layer; and
an interconnect comprising a conductive polymer and continuously extending from the second die layer to the board with a non-circular cross-section shape.

2. The apparatus of claim 1 , in which the first and second die layers comprise a first die stack positioned on a first side of the board, a second die stack comprising at least third and fourth die layers comprise a second die stack, the second die stack positioned on a second side of the board, opposite the first side.

3. The apparatus of claim 1 , in which the first and second die layers vertically aligned with at least two outer edges aligned along different planes, the different planes each perpendicular to the board.

4. The apparatus of claim 1 , in which the interconnect comprises a flexible material.

5. The apparatus of claim 1 , in which the conductive polymer comprises metal particles.

6. The apparatus of claim 1 , in which the first and second die layers are stacked vertically to form uniform outer edges, the interconnect extending in continuous contact with at least one outer edge.

7. The apparatus of claim 6 , in which the interconnect continuously extends around a corner defined by a junction of two uniform outer edges of the first die layer.

8. The apparatus of claim 1 , in which the interconnect comprises linear exterior surfaces from the board to the second die layers.

9. An apparatus comprising:
a die package comprising a board, first die layer, and second die layer positioned in a vertically aligned stack with at least one common edge surface, the board and first and second die layers each separated by a dielectric layer and having a common width and length, the first die layer disposed between the board and second die layer; and
a first interconnect continuously extending from the second die layer to the board with a non-circular cross-section shape; and
a second interconnect continuously extending from the first die layer to the board with a non-circular cross-section shape, the first interconnect positioned between the first die layer and the second interconnect.

10. The apparatus of claim 9 , in which the first and second interconnects are physically separate and overlap.

11. The apparatus of claim 10 , in which the first and second interconnects are separated by a dielectric material.

12. The apparatus of claim 10 , in which the second interconnect extends farther from the board than the first interconnect.

13. The apparatus of claim 9 , in which a third interconnect continuously extends from the board to a third die layer with a non-circular cross-section shape.

14. The apparatus of claim 9 , in which the first and second interconnects are respectively positioned on different outer surfaces of the die layers.

15. The apparatus of claim 10 , in which the first and second interconnects have a common length and dissimilar pathways.

16. The apparatus of claim 9 , wherein the first interconnect continuously contacts an outer edge of the die package and the second interconnect separated from the outer edge of the die package by the first interconnect.

Assignees

• Seagate Technology Llc

Inventors

• Dropps Frank

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title