Methods for fabricating integrated circuits using designs of integrated circuits adapted to directed self-assembly fabrication to form via and contact structures

Patent metadata

Field	Value
Publication number	US-9305834-B1
Application number	US-201414586268-A
Country	US
Kind code	B1
Filing date	Dec 30, 2014
Priority date	Dec 30, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Methods for fabricating integrated circuits using directed self-assembly to form via and contact holes are disclosed. An exemplary method includes determining a natural, hexagonal separation distance L 0 between cylinders formed in a block copolymer (BCP) material during directed self-assembly (DSA) and determining an integrated circuit feature pitch P A according to the following formula: P A =L 0 *(sqrt(3)/2)*n, wherein n is a positive integer. The method further includes generating an integrated circuit layout design better accommodating the natural formation arrangement of polymeric cylinders, wherein integrated circuit features are spaced in accordance with the integrated circuit feature pitch P A and wherein via or contact structures are physically and electrically connected to the integrated circuit features and fabricating the integrated circuit features and the via or contact structures on a semiconductor work-in-process (WIP) in accordance with the integrated circuit layout design, wherein the via or contact structures are fabricated utilizing DSA with BCP material.

First claim

What is claimed is:

1. A method for fabricating an integrated circuit comprising:
determining a natural, hexagonal separation distance L 0 between cylinders formed in a block copolymer (BCP) material during directed self-assembly (DSA);
determining an integrated circuit feature pitch P A according to the following formula:
P A =L 0 *(sqrt(3)/2)* n , wherein n is a positive integer;

generating an integrated circuit layout design wherein integrated circuit features are spaced in accordance with the integrated circuit feature pitch P A and wherein via or contact structures are physically and electrically connected to the integrated circuit features; and
fabricating the integrated circuit features and the via or contact structures on a semiconductor work-in-process (WIP) in accordance with the integrated circuit layout design, wherein the via or contact structures are fabricated utilizing DSA with the BCP material.

2. The method of claim 1 , wherein determining the separation distance L 0 comprises determining the separation distance L 0 between cylinders formed in a BCP material comprising polystyrene-block-polymethylmethacrylate (PS-b-PMMA), polystyrene-block-polybutadiene (PS-b-PB), polystyrene-block-poly(2-vinyl pyridine) (PS-b-P2VP), polystyrene-block-polydimethylsiloxane (PS-b-PDMS), or polystyrene-block-polyethylene oxide (PS-b-PEO).

3. The method of claim 1 , wherein generating the integrated circuit layout design comprises generating the integrated circuit layout design wherein parallel conductive lines of a metallization layer are spaced in accordance with the integrated circuit feature pitch P A .

4. The method of claim 1 , wherein generating the integrated circuit layout design comprises generating the integrated circuit layout design wherein active integrated circuit structures are spaced in accordance with the integrated circuit feature pitch P A .

5. The method of claim 1 , wherein determining the integrated circuit feature pitch P A comprises determining the integrated circuit feature pitch P A according to the formula:
P A =L 0 *(sqrt(3)/2)* n , wherein n is 1.

6. The method of claim 5 , wherein determining the integrated circuit feature pitch P A is performed for integrated circuit features of a first layer of the integrated circuit, wherein the method further comprises determining an integrated circuit feature pitch P B for integrated circuit features of a second layer of the integrated circuit that is disposed above or below the first layer of the integrated circuit, wherein determining the integrated circuit feature pitch P B is performed according to the following formula: P B =(L 0 /2)*m, wherein m is a positive integer selected independently from n, and wherein the method further comprises generating the integrated circuit layout design wherein integrated circuit features of the first layer of the integrated circuit are spaced in accordance with the integrated circuit feature pitch P A and integrated circuit features of the second layer of the integrated circuit are spaced in accordance with the integrated circuit feature pitch P B .

7. The method of claim 6 , wherein determining the integrated circuit feature pitch P B comprises determining the integrated circuit feature pitch P B according to the formula:
P B =( L 0 /2)* m , wherein m is 1.

8. The method of claim 5 , wherein determining the integrated circuit feature pitch P A is performed for integrated circuit features of a first layer of the integrated circuit, wherein the method further comprises determining an integrated circuit feature pitch P B for integrated circuit features of a second layer of the integrated circuit that is disposed above or below the first layer of the integrated circuit, wherein determining the integrated circuit feature pitch P B is performed according to the following formula: P B =L 0 *(sqrt(3)/2)*m, wherein m is a positive integer selected independently from n, and wherein the method further comprises generating the integrated circuit layout design wherein integrated circuit features of the first layer of the integrated circuit are spaced in accordance with the integrated circuit feature pitch P A and integrated circuit features of the second layer of the integrated circuit are spaced in accordance with the integrated circuit feature pitch P B .

9. The method of claim 8 , wherein determining the integrated circuit feature pitch P B comprises determining the integrated circuit feature pitch P B according to the formula:
P B =L 0 *(sqrt(3)/2)* m , wherein m is 1.

10. The method of claim 8 , wherein generating the integrated circuit layout design comprises generating the integrated circuit layout design such that the integrated circuit features of the first layer of the integrated circuit are oriented in a first direction and such that the integrated circuit features of the second layer are oriented in a second direction that is angled with respect to the first direction such that cylinders connected to the first layer of the integrated circuit and separated from one another by the separation distance L 0 are also connected to the second layer of the integrated circuit.

11. The method of claim 10 , wherein generating the integrated circuit layout design comprises generating the integrated circuit layout design such that the integrated circuit features of the second layer are oriented in the second direction that is angled at about 50 to about 70 degrees with respect to the first direction.

12. The method of claim 1 , wherein determining the integrated circuit feature pitch P A comprises determining the integrated circuit feature pitch P A according to the formula:
P A =L 0 *(sqrt(3)/2)* n , wherein n is 2.

13. The method of claim 12 , wherein determining the integrated circuit feature pitch P A is performed for integrated circuit features of a first layer of the integrated circuit, wherein the method further comprises determining an integrated circuit feature pitch P B for integrated circuit features of a second layer of the integrated circuit that is disposed above or below the first layer of the integrated circuit, wherein determining the integrated circuit feature pitch P B is performed according to the following formula: P B =(L 0 /2)*m, wherein m is a positive integer selected independently from n, and wherein the method further comprises generating the integrated circuit layout design wherein integrated circuit features of the first layer of the integrated circuit are spaced in accordance with the integrated circuit feature pitch P A and integrated circuit features of the second layer of the integrated circuit are spaced in accordance with the integrated circuit feature pitch P B .

14. The method of claim 13 , wherein determining the integrated circuit feature pitch P B comprises determining the integrated circuit feature pitch P B according to the formula:
P B =( L 0 /2)* m , wherein m is 1.

15. A method for fabricating an integrated circuit comprising:
determining an integrated circuit feature pitch P A , wherein P A is greater than or equal to a minimum lithography pitch used to pattern confinement wells for enclosing a block copolymer (BCP) material during directed self-assembly (DSA);
generating an integrated circuit layout design wherein integrated circuit features are spaced in accordance with the integrated circuit feature pitch P A and wherein via or contact structures are physically and electrically connected to the integrated circuit features; and
fabricating the integrated circuit features and the via

Assignees

• Globalfoundries Inc

Inventors

• Latypov Azat
• Xu Ji

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/055

  by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/032 Primary

  of conductive barrier, adhesion or liner layers · CPC title

• H10D89/10

  Integrated device layouts · CPC title