Page buffer connections and determining pass/fail condition of memories

Patent metadata

Field	Value
Publication number	US-9305660-B2
Application number	US-201314012602-A
Country	US
Kind code	B2
Filing date	Aug 28, 2013
Priority date	Oct 1, 2010
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Apparatus and methods for determining pass/fail condition of memories facilitate array efficiencies. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory.

First claim

What is claimed is:

1. A method of operating a memory device, comprising:
precharging a plurality of common lines, each common line connected in parallel to each page buffer of a corresponding plurality of page buffers, wherein each page buffer of the corresponding plurality of page buffers for a given common line corresponds to a particular bit position of a plurality of bytes;
sensing a voltage on each of the common lines;
indicating a pass of a common line of the plurality of common lines when each page buffer to which it is connected indicates as a pass bit; and
indicating a fail of a common line of the plurality of common lines when any page buffer to which it is connected indicates as a fail bit.

2. The method of claim 1 , and further comprising:
combining each of the plurality of common lines in an OR circuit, wherein a logic 0 at an output of the OR circuit indicates a passing condition of the plurality of bytes of the memory device, and wherein a logic 1 at the output of the OR circuit indicates a failing condition of the plurality of bytes of the memory device.

3. The method of claim 1 , wherein indicating a fail further comprises discharging at least one of the plurality of common lines.

4. The method of claim 3 , wherein discharging comprises discharging any of the plurality of common lines that has at least one page buffer connected thereto that is selectively coupled to a memory cell that fails verification.

5. The method of claim 1 , wherein indicating a pass further comprises not discharging any of the plurality of common lines.

6. The method of claim 1 , and further comprising combining pass/fail data for each of the plurality of common lines to indicate a page pass/fail status.

7. The method of claim 1 , and further comprising setting a program latch for each memory cell that passes verification.

8. The method of claim 1 , and further comprising identifying a specific failed bit on a particular common line of the plurality of common lines.

9. The method of claim 8 , wherein identifying a specific failed bit further comprises:
precharging the particular common line;
inhibiting all columns coupled to the page buffers connected to the particular common line except one; and
discharging the particular common line when the page buffer coupled to the one uninhibited column and connected to the particular common line indicates a failing bit.

10. The method of claim 1 , and further comprising:
detecting a fail condition for a page buffer.

11. The method of claim 10 , wherein detecting a fail condition comprises:
inhibiting all columns not selectively coupled to the page buffer; and
performing verification on a memory cell selectively coupled to the page buffer.

12. A memory device, comprising:
an array of memory cells; and
circuitry for control and/or access of the array of memory cells, the control circuitry configured to perform a method comprising:
precharging a plurality of common lines, each common line connected in parallel to each page buffer of a corresponding plurality of page buffers, wherein each page buffer of the corresponding plurality of page buffers for a given common line corresponds to a particular bit position of a plurality of bytes;
sensing a voltage on each of the common lines;
indicating a pass of a common line of the plurality of common lines when each page buffer to which it is connected indicates as a pass bit; and
indicating a fail of a common line of the plurality of common lines when any page buffer to which it is connected indicates as a fail bit.

13. The memory device of claim 12 , wherein the control circuitry is further configured to combine each of the plurality of common lines in an OR circuit, and to indicate a passing condition of the plurality of bytes of the memory device when an output of the OR circuit is a logic 0.

14. The memory device of claim 13 , wherein the control circuitry is further configured to indicate a failing condition of the plurality of bytes of the memory device when an output of the OR circuit is a logic 1.

15. The memory device of claim 12 , wherein the control circuitry is further configured to set a program latch for each memory cell that passes verification.

16. The memory device of claim 12 , wherein the control circuitry is further configured to identify a specific failed bit on a particular common line of the plurality of common lines.

17. The method of claim 16 , wherein the control circuitry is further configured to identify the specific failed bit by precharging the particular common line, selectively inhibiting all page buffers along the particular common line except one, and discharging the particular common line when the bit on the particular common line and the not inhibited page buffer is a failing bit.

18. A memory device, comprising:
an array of memory cells;
circuitry for control and/or access of the array of memory cells;
a plurality of page buffers;
a plurality of common lines, each common line connected in parallel to a corresponding group of page buffers of the plurality of page buffers corresponding to a respective bit position of a plurality of bytes; and
a plurality of pass/fail circuits, each of the plurality of pass/fail circuits connected to a respective one of the plurality of common lines.

19. The memory device of claim 18 , and further comprising an OR circuit connected to each of the plurality pass/fail circuits.

20. A memory, comprising:
an array of memory cells;
circuitry for control and/or access of the array of memory cells;
a plurality of page buffers;
a plurality of common lines, each common line connected in parallel to one bit of each of the plurality of page buffers of a respective rank corresponding to a page of the array of memory cells;
a plurality of check transistors, a check transistor for each page buffer, each check transistor connected to one of the plurality of common lines through one of a plurality of program transistors;
a plurality of latches, a latch connected to the gate of each program transistor; and
a plurality of pass/fail circuits, a pass/fail circuit connected to each of the plurality of common lines.

21. The memory of claim 20 , and further comprising an OR circuit connected to each of the plurality pass/fail circuits.

Assignees

• Micron Technology Inc

Inventors

• Moschiano Violante
• Santin Giovanni

Classifications

• G11C2029/0409

  Online test · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title