Program verify word line ramping delay for lower current consumption mode
US-2024395343-A1 · Nov 28, 2024 · US
US9305650B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9305650-B2 |
| Application number | US-201414181427-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 14, 2014 |
| Priority date | Feb 14, 2014 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through a tunneling dielectric layer. The charge storage region includes a floating gate charged by tunneled carriers from the channel region. Charge retention is facilitated by the band offset between the charge storage region and the tunneling dielectric layer.
Opening claim text (preview).
What is claimed is: 1. A field-effect floating gate memory device comprising: a channel region having a conductivity type and adjoining an electrically insulating substrate; doped source and drain regions operatively associated with and having the same conductivity type as the channel region; a control gate; a floating gate for storing carriers from the channel region, the floating gate being positioned between the channel region and the control gate, the floating gate havin…
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Electricity · mapped topic
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