Frequency power manager

Patent metadata

Field	Value
Publication number	US-9305632-B2
Application number	US-201313901511-A
Country	US
Kind code	B2
Filing date	May 23, 2013
Priority date	Apr 29, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

First claim

What is claimed is:

1. A method of a hardware module for controlling a power mode of a plurality of modules, comprising:
receiving an indication of a desired operational frequency;
determining to switch from a first power mode to a second power mode based on the received indication of the desired operational frequency, the first power mode being associated with a first set of modules of the plurality of modules, the second power mode being associated with a second set of modules of the plurality of modules, the second power mode corresponding to the desired operational frequency;
enabling modules in the second set of modules that are unassociated with the first power mode;
stopping traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode;
routing traffic through the second set of modules; and
disabling modules in the first set of modules that are unassociated with the second power mode,
wherein the plurality of modules includes at least one of a calibrated delay circuit (CDC), an input receiver, a low-dropout (LDO) regulator, a current-to-voltage converter, a phase lock loop (PLL), a bias current generator, or a reference voltage generator.

2. The method of claim 1 , wherein the enabling the modules comprises turning on the modules and the disabling the modules comprises turning off the modules.

3. The method of claim 1 , wherein the enabling the modules comprises changing a state of the modules from a lower-power standby state to a higher-power operational state, and the disabling the modules comprises changing a state of the modules from a higher-power operational state to a lower-power standby state.

4. The method of claim 1 , wherein the traffic is stopped for approximately 10 ns to 20 ns.

5. The method of claim 1 , further comprising waiting for the time period until the second set of modules reaches a steady state.

6. The method of claim 1 , wherein the hardware module and the first and second sets of modules are within a double data rate (DDR) physical (PHY) hardware module.

7. The method of claim 1 , wherein the plurality of modules is associated with a double data rate (DDR) dynamic random access memory (DRAM).

8. The method of claim 1 , wherein the plurality of modules comprises a first CDC and a second CDC in parallel with the first CDC, the first set of modules comprises the first CDC, and the second set of modules comprises the second CDC, wherein the modules that are enabled in the second set of modules that are unassociated with the first power mode comprise the second CDC, and the modules that are disabled in the first set of modules that are unassociated with the second power mode comprise the first CDC.

9. The method of claim 8 , wherein the second CDC supports a higher power mode than the first CDC.

10. The method of claim 8 , wherein the second CDC supports a lower power mode than the first CDC.

11. The method of claim 1 , wherein the plurality of modules comprises a first input receiver and a second input receiver in parallel with the first input receiver, the first set of modules comprises the first input receiver, and the second set of modules comprises the second input receiver, wherein the modules that are enabled in the second set of modules that are unassociated with the first power mode comprise the second input receiver, and the modules that are disabled in the first set of modules that are unassociated with the second power mode comprise the first input receiver.

12. The method of claim 11 , wherein the second input receiver supports a higher power mode than the first input receiver.

13. The method of claim 11 , wherein the second input receiver supports a lower power mode than the first input receiver.

14. The method of claim 1 , wherein the first power mode comprises a ultra-low power mode and the second power mode comprises a low power mode, the first set of modules comprises a low-power CDC and a low-power input receiver the second set of modules comprises the low-power CDC and a medium-power input receiver, wherein the modules that are enabled in the second set of modules that are unassociated with the first power mode comprise the medium-power input receiver, and the modules that are disabled in the first set of modules that are unassociated with the second power mode comprise the low-power input receiver.

15. The method of claim 1 , wherein the first power mode comprises a ultra-low power mode and the second power mode comprises a medium performance mode, the first set of modules comprises a low-power CDC and a low-power input receiver, the second set of modules comprises a high-power CDC, the current-to-voltage converter, the PLL, the bias current generator, and a medium-power input receiver, wherein the modules that are enabled in the second set of modules that are unassociated with the first power mode comprise the second set of modules, and the modules that are disabled in the first set of modules that are unassociated with the second power mode comprise the first set of modules.

16. The method of claim 1 , wherein the first power mode comprises a ultra-low power mode and the second power mode comprises a high performance mode, the first set of modules comprises a low-power CDC and a low-power input receiver, the second set of modules comprises a high-power CDC, the current-to-voltage converter, the PLL, the LDO regulator, the bias current generator, the reference voltage generator, and a high-power input receiver, wherein the modules that are enabled in the second set of modules that are unassociated with the first power mode comprise the second set of modules, and the modules that are disabled in the first set of modules that are unassociated with the second power mode comprise the first set of modules.

17. The method of claim 1 , wherein the first power mode comprises a low power mode and the second power mode comprises an ultra-low power mode, the first set of modules comprises a low-power CDC and a medium-power input receiver, the second set of modules comprises the low-power CDC and a low-power input receiver, wherein the modules that are enabled in the second set of modules that are unassociated with the first power mode comprise the low-power input receiver, and the modules that are disabled in the first set of modules that are unassociated with the second power mode comprise the medium-power input receiver.

18. The method of claim 1 , wherein the first power mode comprises a low power mode and the second power mode comprises a medium performance mode, the first set of modules comprises a low-power CDC and a medium-power input receiver, the second set of modules comprises a high-power CDC, the current-to-voltage converter, the PLL, the bias current generator, and the medium-power input receiver, wherein the modules that are enabled in the second set of modules that are unassociated with the first power mode comprise the high-power CDC, the current-to-voltage converter, the PLL, and the bias current generator, and the modules that are disabled in the first set of modules that are unassociated with the second power mode comprise the low-power CDC.

19. The method of claim 1 , wherein the first power mode comprises a low power mode and the second power mode comprises a high performance mode, the first set of modules comprises a low-power CDC and a medium-power input receiver, the second set of modules comprises a high-power CDC, the current-to-voltage converter, the PLL, the LDO regul

Assignees

• Qualcomm Inc

Inventors

• Syed Zeeshan Shafaq
• Chen Nan
• Xu Yong
• Fertsch Michael Thomas
• Andreev Boris Dimitrov
• Chen Zhiqin
• Kwon Chang Ki

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• Y02B60/32

  Cross-Sectional Technologies · mapped topic

• Y02B60/1282

  Cross-Sectional Technologies · mapped topic