Semiconductor memory cell array having fast array area and semiconductor memory including the same

Patent metadata

Field	Value
Publication number	US-9305616-B2
Application number	US-201313943790-A
Country	US
Kind code	B2
Filing date	Jul 17, 2013
Priority date	Jul 17, 2012
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A semiconductor memory cell array is provided which includes a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed. The first and second memory cell array areas are accessed by addressing of a DRAM controller.

First claim

What is claimed is:

1. A semiconductor memory cell array, comprising:
a first memory cell array area including a first group of memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and
a second memory cell array area including a second group of memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed faster than the first operating speed,
wherein the semiconductor memory cell array is configured such that the first and second memory cell array areas are accessed by addressing of a dynamic random access memory (DRAM) controller, and
wherein the second memory cell array area is positioned between an input-output sense amplifier and the first memory cell array area, such that the second memory cell array area is disposed to be closer to the input-output sense amplifier than the first memory cell array area is to the input-output sense amplifier.

2. The semiconductor memory cell array of claim 1 , wherein the first group of memory cells and the second group of memory cells are different types of cells.

3. The semiconductor memory cell array of claim 2 , wherein the first group of memory cells are formed of DRAM cells, and the second group of memory cells are formed using a bit line sense amplifier.

4. The semiconductor memory cell array of claim 2 , wherein the first group of memory cells are formed of DRAM cells, and the second group of memory cells are static random access memory (SRAM) cells.

5. The semiconductor memory cell array of claim 1 , wherein the first group of memory cells and the second group of memory cells are same types of cells.

6. The semiconductor memory cell array of claim 5 , wherein the first group of memory cells are DRAM cells having normal word line loading, and the second group of memory cells are DRAM cells having loading smaller than the normal word line loading.

7. The semiconductor memory cell array of claim 5 , wherein the first group of memory cells are DRAM cells having normal bit line loading, and the second group of memory cells are DRAM cells having loading smaller than the normal bit line loading.

8. The semiconductor memory cell array of claim 5 , wherein the first group of memory cells are SRAM cells having normal word line loading, and the second of group memory cells are SRAM cells having loading smaller than the normal word line loading.

9. The semiconductor memory cell array of claim 5 , wherein the first group of memory cells are SRAM cells having normal bit line loading, and the second group of memory cells are SRAM cells having loading smaller than the normal bit line loading.

10. A semiconductor memory cell array, comprising:
a first memory cell array area including a first group of memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed, the first memory cell array area including slow memory cell arrays alternately arranged between a plurality of bit line sense amplifiers; and
a second memory cell array area including a second group of memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed faster than the first operating speed, an input-output sense amplifier being interposed between the first memory cell array area and the second memory cell array area.

11. The semiconductor memory cell array of claim 10 , wherein a normally accessed address is assigned to the first memory cell array area and a highly accessed address is assigned to the second memory cell array area.

12. The semiconductor memory cell array of claim 10 , wherein the first memory cell array area is assigned to a bandwidth sensitive load and the second memory cell array area is assigned to a latency sensitive load.

13. The semiconductor memory cell array of claim 10 , wherein the first memory cell array area is assigned to an isolated address space and the second memory cell array area is assigned to a shared address space.

14. The semiconductor memory cell array of claim 10 , wherein the first memory cell array area is configured to be accessed using an extended address and the second memory cell array area is configured to be accessed using a basic address.

15. The semiconductor memory cell array of claim 10 , wherein the first memory cell array area is configured to be accessed using a high address of a basic address and the second memory cell array area is configured to be accessed using a low address of the basic address.

16. The semiconductor memory cell array of claim 10 , wherein the second memory cell array area is disposed to be separated into a plurality of regions according to an access speed.

17. The semiconductor memory cell array of claim 10 , wherein the second memory cell array area is connected with a memory controller via a dedicated data bus and a dedicated command bus.

18. A semiconductor memory cell array, comprising:
a first memory cell array area including a first group of memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and
a second memory cell array area including a second group of memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed faster than the first operating speed,
wherein the semiconductor memory cell array is configured such that the first memory cell array area and the second memory cell array area are accessed by addressing of a DRAM controller and have different bit line loading from each other, and
wherein the second memory cell array area is connected with a column repair circuit and is configured to be used as a fail address memory to store fail column addresses for a column repair.

19. The semiconductor memory cell array of claim 18 , wherein the first memory cell array area and the second memory cell array area share a word line enable signal of a row decoder to have the same word line loading.

20. The semiconductor memory cell array of claim 18 , wherein the first memory cell array area and the second memory cell array area are connected to separated word lines and have different word line loading.

21. The semiconductor memory cell array of claim 18 , wherein the second memory cell array area is connected with a refresh control circuit and is configured to be used as a refresh information memory to store refresh strong/weak data for a refresh skip operation.

22. The semiconductor memory cell array of claim 21 , wherein the refresh strong/weak data is stored in a flag form and is refresh information on a current or next row address.

23. The semiconductor memory cell array of claim 18 , wherein an address distribution of the second memory cell array area has a continuous address distribution.

24. The semiconductor memory cell array of claim 18 , wherein an address distribution of the second memory cell array area is placed between address distributions of the first memory cell array area and has a discontinuous address distribution.

25. The semiconductor memory cell array of claim 24 , wherein address intervals of the second memory cell array area are regular or irregular.

26. A semiconductor memory cell array, comprising:
a first memory cell array including a first group of memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and
a second memory cell array including a second group of memory cells arranged in the chip in a m

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Haksoo
• Kim Dae-Hyun
• Kang Uksong
• Park Chulwoo
• Choi Joosun
• Choi Hyojin

Classifications

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G11C29/783

  with refresh of replacement cells, e.g. in DRAMs · CPC title

• G06F12/0223

  User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title