Netlist cell identification and classification to reduce power consumption

Patent metadata

Field	Value
Publication number	US-9305128-B2
Application number	US-201314102167-A
Country	US
Kind code	B2
Filing date	Dec 10, 2013
Priority date	Apr 10, 2008
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

First claim

What is claimed is:

1. In a computer implemented synthesis system, a method for modifying netlist cells of an integrated circuit device to reduce power consumption, comprising:
accessing a circuit netlist, within an electronic system, the circuit netlist representing an integrated circuit design to be realized in physical form; and
modifying a plurality of cells of the netlist by using a per cell iterative search, wherein the iterative search functions by:
determining those cells of the circuit netlist that are coupled to an always on power domain;
determining those cells of the circuit netlist that are coupled to a second power domain, wherein the second power domain is a sleep mode enabled power domain; and
configuring those cells that are coupled to the second power domain to be shut down when the integrated circuit device enters sleep mode.

2. The method of claim 1 , wherein the always on power domain is configured to retain power and selected device state data when the second power domain is shut down.

3. The method of claim 1 , those cells that are coupled to the second power domain are shut down with reduced leakage current when power to the second power domain is shut down.

4. The method of claim 1 , wherein the per cell iterative search functions by examining each cell of the circuit netlist and altering an examined cell upon determining whether the examined cell is coupled to the second power domain.

5. The method of claim 4 , wherein the per cell iterative search is complete when each cell of the circuit netlist is examined and no alterations are performed.

6. The method of claim 1 , wherein the per cell iterative search is initiated at a functional block within the second power domain and traces those cells that cascade from the functional block.

7. The method of claim 1 , wherein the per cell iterative search is initiated at an input output pad providing functionality for the second power domain and traces those cells that cascade from the input output pad.

8. The method of claim 1 , wherein the per cell iterative search is configured to ensure cells providing functionality for the always on power domain are not altered to draw power from the second power domain.

9. In a computer implemented synthesis system, a method for modifying netlist cells of an integrated circuit device to reduce power consumption, comprising:
accessing a circuit netlist, within an electronic system, the circuit netlist representing an integrated circuit design to be realized in physical form; and
modifying a plurality of cells of the netlist by using a per cell iterative search, wherein the iterative search functions by:
determining those cells of the circuit netlist that are coupled to an always on power domain;
determining those cells of the circuit netlist that are coupled to a second domain, wherein the second domain is a sleep mode enabled power domain;
configuring those cells that are coupled to the second power domain to be shut down when the integrated circuit device enters sleep mode; and
wherein the always on power domain is configured to retain power and selected device state data when the second power domain is shut down.

10. The method of claim 9 , those cells that are coupled to the second power domain are shut down with reduced leakage current when power to the second power domain is shut down.

11. The method of claim 9 , wherein the per cell iterative search functions by examining each cell of the circuit netlist and altering an examined cell upon determining whether the examined cell is coupled to the second power domain.

12. The method of claim 11 , wherein the per cell iterative search is complete when each cell of the circuit netlist is examined and no alterations are performed.

13. The method of claim 9 , wherein the per cell iterative search is initiated at a functional block within the second power domain and traces those cells that cascade from the functional block.

14. The method of claim 9 , wherein the per cell iterative search is initiated at an input output pad providing functionality for the second power domain and traces those cells that cascade from the input output pad.

15. The method of claim 9 , wherein the per cell iterative search is configured to ensure cells providing functionality for the always on power domain are not altered to draw power from the second power domain.

16. In a computer implemented synthesis system, a method for modifying netlist cells of an integrated circuit device to reduce power consumption, comprising:
accessing a circuit netlist, within an electronic system, the circuit netlist representing an integrated circuit design to be realized in physical form; and
modifying a plurality of cells of the netlist by using a per cell iterative search, wherein the iterative search functions by:
determining those cells of the circuit netlist that are coupled to an always on power domain;
determining those cells of the circuit netlist that are coupled to a second power domain, wherein the second domain is a sleep mode enabled power domain;
configuring those cells that are coupled to the second power domain to be shut down when the integrated circuit device enters sleep mode; and
wherein those cells that are coupled to the second power domain are shut down with reduced leakage current when power to the second power domain is shut down.

17. The method of claim 16 , wherein the always on power domain is configured to retain power and selected device state data when the second power domain is shut down.

18. The method of claim 16 , wherein the per cell iterative search functions by examining each cell of the circuit netlist and altering an examined cell upon determining whether the examined cell is coupled to the second power domain.

19. The method of claim 18 , wherein the per cell iterative search is complete when each cell of the circuit netlist is examined and no alterations are performed.

20. The method of claim 16 , wherein the per cell iterative search is initiated at a functional block within the second power domain and traces those cells that cascade from the functional block.

21. The method of claim 16 , wherein the cells that are coupled to the second power domain comprises respective functional portions of the integrated circuit design.

Assignees

• Nvidia Corp

Inventors

• Verbeure Tom

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F17/5081

  Physics · mapped topic