Memory control device, storage device, and memory control method

Patent metadata

Field	Value
Publication number	US-9304952-B2
Application number	US-201113205193-A
Country	US
Kind code	B2
Filing date	Aug 8, 2011
Priority date	Oct 21, 2010
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.

First claim

What is claimed is:

1. A memory system comprising:
a nonvolatile memory including a plurality of memory areas, the plurality of memory areas being connected to a plurality of channels; and
a controller controlling the nonvolatile memory, wherein the controller is configured to:
in response to a reading from any one of the plurality of memory areas being completed,
when a first processing and a second processing are ready to be performed, the first processing being a parallel writing to the plurality of memory areas, the second processing being a reading from any one of the plurality of memory areas,
give higher priority to the first processing over the second processing as a next command to be executed; and

in response to a parallel writing to the plurality of memory areas being completed,
when the first processing and the second processing are ready to be performed,
give higher priority to the second processing over the first processing as a next command to be executed,

wherein, in a case that the first processing and the second processing are ready to be performed, the controller alternately performs the first processing and the second processing one after the other.

2. The memory system according to claim 1 , wherein
the controller is configured to generate error correction codes based on data to be written to the plurality of memory areas, and write the generated error correction codes to one memory area among the plurality of memory areas, when the parallel writing is performed.

3. A method for controlling a nonvolatile memory, the nonvolatile memory including a plurality of memory areas, the plurality of memory areas being connected to a plurality of channels, the method comprising:
in response to a reading from any one of the plurality of memory areas being completed,
when a first processing and a second processing are ready to be performed, the first processing being a parallel writing to the plurality of memory areas, the second processing being a reading from any one of the plurality of memory areas,
giving higher priority to the first processing over the second processing as a next command to be executed; and

in response to a parallel writing to the plurality of memory areas being completed,
when the first processing and the second processing are ready to be performed,
giving higher priority to the second processing over the first processing as a next command to be executed,

wherein, in a case that the first processing and the second processing are ready to be performed, alternately performing the first processing and the second processing one after the other.

4. The method according to claim 3 , further comprising generating error correction codes based on data to be written to the plurality of memory areas, and writing the generated error correction codes to one memory area among the plurality of memory areas, when the parallel writing is performed.

5. A memory system comprising:
a memory including a plurality of memory areas; and
a controller controlling the memory, wherein
the controller is configured to:
in a case that a read process from any one of the plurality of memory areas is completed, and when a next read process and a next parallel write process are ready,
perform the next parallel write process to the plurality of memory areas before the next read process; and

in a case that a parallel write process is completed, and when the next read process and next parallel write process are ready,
perform the next read process before the next parallel write process,

wherein, in a case that the parallel write process and the read process are ready to be performed, the controller alternately performs the parallel write process and the read process one after the other.

Assignees

• Nango Takahiro
• Moro Hiroyuki
• Fukuda Tohru
• Toshiba Kk

Inventors

• Nango Takahiro
• Moro Hiroyuki
• Fukuda Tohru

Classifications

• G06F13/1642 Primary

  with request queuing · CPC title

• G11B20/18

  Error detection or correction; Testing {, e.g. of drop-outs} · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title