Decoding with log likelihood ratios stored in a controller

Patent metadata

Field	Value
Publication number	US-9304851-B2
Application number	US-201314136380-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Nov 27, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values.

First claim

The invention claimed is:

1. An apparatus comprising:
an interface configured to process a plurality of read/write operations to/from a memory; and
a control circuit configured to (i) store a plurality of groups in one or more lookup tables, wherein each of the plurality of groups comprises a plurality of sets and each of the plurality of sets comprises a plurality of log likelihood ratio values, (ii) read a codeword from the memory, (iii) read a first set of the plurality of sets in an initial group of the plurality of groups from the one or more lookup tables, (iv) attempt to decode the codeword based on the plurality of log likelihood ratio values in the first set in the initial group, and (v) in response to non-convergence with the plurality of log likelihood ratio values in the first set in the initial group, (a) read a second set of the plurality of sets in the initial group from the one or more lookup tables and (b) attempt to decode the codeword based on the plurality of log likelihood ratio values in the second set in the initial group.

2. The apparatus according to claim 1 , wherein the control circuit is further configured to read a third set of the plurality of sets in the initial group from the one or more lookup tables in response to non-convergence with the plurality of log likelihood ratio values in the second set in the initial group.

3. The apparatus according to claim 1 , wherein the control circuit is further configured to reread the codeword from the memory in response to non-convergence with the plurality of boa likelihood ratio values in the initial group.

4. The apparatus according to claim 3 , wherein the control circuit is further configured to read an additional set of the plurality of sets in an additional group of the plurality of groups from the one or more lookup tables in response to the reread of the codeword from the memory.

5. The apparatus according to claim 3 , wherein the control circuit is further configured to generate a plurality of patterns corresponding to a plurality of bits in the codeword based on both the read and the reread of the codeword from the memory.

6. The apparatus according to claim 5 , wherein the control circuit is further configured to select the plurality of log likelihood ratio values used to attempt to decode the codeword based on the plurality of patterns.

7. The apparatus according to claim 1 , wherein each of the plurality of groups comprises (i) a normal set of the plurality of log likelihood ratio values and (ii) a plurality of compensated sets of the plurality of log likelihood ratio values that are compensated relative to the normal set.

8. The apparatus according to claim 1 , wherein (i) each of the plurality of sets is divided into a plurality of pages, (ii) each of the plurality of pages is divided into a corresponding subset of the plurality of log likelihood ratio values, and (iii) a respective one of the plurality of log likelihood ratio values corresponds to each of a plurality of possible patterns created by a plurality of reads of the codeword from the memory.

9. The apparatus according to claim 1 , wherein the interface and the control circuit are part of a solid-state drive controller.

10. A method for decoding with a plurality of log likelihood ratio values stored in a control circuit, comprising the steps of:
storing a plurality of groups in one or more lookup tables in the control circuit, wherein each of the plurality of groups comprises a plurality of sets and each of the plurality of sets comprises the plurality of log likelihood ratio values;
reading a codeword from a memory;
reading a first set of the plurality of sets in an initial group of the plurality of groups from the one or more lookup tables;
attempting to decode the codeword based on the plurality of log likelihood ratio values in the first set in the initial group; and
in response to non-convergence with the plurality of log likelihood ratio values in the first set in the initial group, (a) reading a second set of the plurality of sets in the initial group from the one or more lookup tables and (b) attempting to decode the codeword based on the plurality of log likelihood ratio values in the second set in the initial group.

11. The method according to claim 10 , further comprising the step of:
reading a third set of the plurality of sets in the initial group from the one or more lookup tables in response to non-convergence with the plurality of log likelihood ratio values in the second set in the initial group.

12. The method according to claim 10 , further comprising the step of:
rereading the codeword from the memory in response to non-convergence with the plurality of log likelihood ratio values in the initial group.

13. The method according to claim 12 , further comprising the step of:
reading an additional set of the plurality of sets in an additional group of the plurality of groups from the one or more lookup tables in response to the reread of the codeword from the memory.

14. The method according to claim 12 , further comprising the step of:
generating a plurality of patterns corresponding to a plurality of bits in the codeword based on both the read and the reread of the codeword from the memory.

15. The method according to claim 14 , further comprising the step of:
selecting the plurality of log likelihood ratio values used to decode the codeword based on the plurality of patterns.

16. The method according to claim 10 , wherein each of the plurality of groups comprises (i) a normal set of the plurality of log likelihood ratio values and (ii) a plurality of compensated sets of the plurality of log likelihood ratio values that are compensated relative to the normal set.

17. The method according to claim 10 , wherein (i) each of the plurality of sets is divided into a plurality of pages, (ii) each of the plurality of pages is divided into a corresponding subset of the plurality of log likelihood ratio values, and (iii) a respective one of the plurality of log likelihood ratio values corresponds to each of a plurality of possible patterns created by a plurality of reads of the codeword from the memory.

18. The method according to claim 10 , wherein the steps are performed in a solid-state drive controller.

19. An apparatus comprising:
a memory configured to store data; and
a controller configured to (i) process a plurality of input/output requests to read/write to/from the memory, (ii) store a plurality of groups in one or more lookup tables, wherein each of the plurality of groups comprises a plurality of sets and each of the plurality of sets comprises a plurality of log likelihood ratio values, (iii) read a codeword from the memory, (iv) read a first set of the plurality of sets in an initial group of the plurality of groups from the one or more lookup tables, (v) attempt to decode the codeword based on the plurality of log likelihood ratio values in the first set in the initial group, and (vi) in response to non-convergence with the plurality of log likelihood ratio values in the first set in the initial group, (a) read a second set of the plurality of sets in the initial group from the one or more lookup tables and (b) attempt to decode the codeword based on the plurality of log likelihood ratio values in the second set in the initial group.

20. The apparatus according to claim 19 , wherein the memory and the controller are part of a solid-state drive.

Assignees

• Seagate Technology Llc

Inventors

• Wu Yunxiang
• Chen Zhengang
• Haratsch Erich F

Classifications

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title