CPU independent graphics scheduler for performing scheduling operations for graphics hardware

Patent metadata

Field	Value
Publication number	US-9304813-B2
Application number	US-201213552122-A
Country	US
Kind code	B2
Filing date	Jul 18, 2012
Priority date	Jul 18, 2012
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A computing device for performing scheduling operations for graphics hardware is described herein. The computing device includes a central processing unit (CPU) that is configured to execute an application. The computing device also includes a graphics scheduler configured to operate independently of the CPU. The graphics scheduler is configured to receive work queues relating to workloads from the application that are to execute on the CPU and perform scheduling operations for any of a number of graphics engines based on the work queues.

First claim

What is claimed is:

1. A computing device, comprising:
a central processing unit (CPU) configured to execute an application;
graphics hardware comprising graphics engines configured to process graphics tasks received from the application executing on the CPU;
a graphics scheduler to select one of the graphics engines to execute each of a plurality of workloads, the graphics scheduler comprising a graphics microcontroller and a shim layer and configured to operate independently of the CPU and the graphics hardware, the graphics scheduler to:
receive interrupts from the graphics hardware and the CPU;
receive work queues comprising the graphics tasks from the application; and
schedule the processing of the graphics tasks by the selected graphics engine in response to the interrupts by writing to a runlist port register of the graphics hardware;
the shim layer to intercept interrupts from the graphics hardware and the CPU and forward the interrupts to the graphics microcontroller.

2. The computing device of claim 1 , wherein the graphics hardware comprises graphics engines configured to execute specific types of workloads.

3. The computing device of claim 1 , wherein the graphics scheduler is configured to access physical memory spaces relating to any of the work queues.

4. The computing device of claim 3 , wherein, to access the physical memory spaces relating to any of the work queues, the graphics scheduler is configured to translate graphics virtual memory addresses into corresponding physical memory addresses via an input/output memory management unit (IOMMU).

5. The computing device of claim 1 , wherein the graphics scheduler is configured to perform scheduling operations for a display engine based on the work queues.

6. The computing device of claim 1 , comprising a radio, wherein the radio is communicatively coupled to the CPU.

7. The computing device of claim 1 , comprising a display, wherein the display is communicatively coupled to the CPU.

8. The computing device of claim 1 , wherein the graphics scheduler is configured to operate independently of a power state of the CPU.

9. A method for performing scheduling operations for graphics hardware comprising graphics engines, the method comprising:
receiving, at a graphics scheduler of a computing device, work queues comprising graphics tasks from an application executing on a central processing unit (CPU) of the computing device;
receiving, at a shim layer of the graphics scheduler, interrupts from the graphics hardware configured to process the graphics tasks received from the application;
forwarding the interrupts from the shim layer to a graphics microcontroller of the graphics scheduler;
scheduling the processing of the graphics tasks by a selected one of the graphics engines in response to the interrupts by writing to a runlist port register of the graphics hardware, wherein the scheduling is performed via the graphics microcontroller independently of the CPU.

10. The method of claim 9 , wherein scheduling the processing of the graphics tasks comprises determining an order of executing workloads for the graphics hardware.

11. The method of claim 9 , comprising accessing physical memory spaces relating to any of the work queues by translating graphics virtual memory addresses into corresponding physical memory addresses.

12. The method of claim 9 , comprising notifying the application upon successful completion of a workload by the graphics hardware.

13. At least one non-transitory machine readable medium having instructions stored therein that, in response to being executed on a computing device, cause the computing device to:
receive, at a graphics scheduler, work queues comprising graphics tasks from an application executing on a central processing unit (CPU);
receive, at a shim layer of the graphics scheduler, interrupts from a graphics hardware configured to process the graphics tasks received from the application, the graphics hardware comprising graphics engines;
forward the interrupts from the shim layer to a graphics microcontroller of the graphics scheduler; and
schedule the processing of the graphics tasks by the graphics hardware in response to the interrupts by selecting graphics engines to execute each of the graphics tasks and writing to a runlist port register of the selected graphics engines, wherein the scheduling is performed via the graphics scheduler independently of the CPU.

14. The at least one non-transitory machine readable medium of claim 13 , wherein scheduling the processing of the graphics tasks by the graphics hardware comprises determining an order of executing workloads for each of the graphics engines.

15. The at least one non-transitory machine readable medium of claim 13 , wherein the instructions cause the computing device to notify the application upon successful completion of a workload by a corresponding graphics engine.

Assignees

• Vembu Balaji
• Navale Aditya
• Ramadoss Murali
• Standring David I
• Bala Kritika
• Intel Corp

Inventors

• Vembu Balaji
• Navale Aditya
• Ramadoss Murali
• Standring David I
• Bala Kritika

Classifications

• Y02B60/144

  Cross-Sectional Technologies · mapped topic

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title