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Cache prefetch for deterministic finite automaton instructions
US9304768B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9304768-B2 |
| Application number | US-201213718966-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 18, 2012 |
| Priority date | Dec 18, 2012 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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Abstract
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In a DFA scanning engine used to match regular expressions or similar rules, instructions to execute DFA state transitions are accessed through an instruction cache. Each DFA instruction may indicate varying numbers of transitions or branches from a current state. The cache pre-fetches a requested number of additional instructions consecutively following an accessed instruction. The DFA engine accesses an instruction from the cache corresponding to a state within a small number of transitions from the root state. When a low-branching instruction is executed to access a next instruction from the root state, or when a low-branching instruction is executed to access a next instruction from the cache, a fixed or configurable pre-fetch length is requested. Some instructions such as low-branching instructions may contain a pre-fetch hint.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of pre-fetching instructions to an instruction cache for a Deterministic Finite Automaton (DFA) engine during a DFA descent, said DFA descent comprising a transition depth and a branching value, said method comprising: accessing an instruction from an instruction cache; and pre-fetching a number of instructions immediately following the accessed instruction to the instruction cache, wherein the number of instructions is selected based on at least…
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Physics · mapped topic
- G06F9/30047Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9304768B2 cover?
- In a DFA scanning engine used to match regular expressions or similar rules, instructions to execute DFA state transitions are accessed through an instruction cache. Each DFA instruction may indicate varying numbers of transitions or branches from a current state. The cache pre-fetches a requested number of additional instructions consecutively following an accessed instruction. The DFA engine …
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F9/30047. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).