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US-2024414666-A1 · Dec 12, 2024 · US
Techniques for rate governing of a display data stream
US9304731B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9304731-B2 |
| Application number | US-201113997237-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 21, 2011 |
| Priority date | Dec 21, 2011 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
Techniques for rate governing of a display data stream are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module comprising a differential analyzer. In some embodiments, the graphics management module may be operative on the processor circuit to determine a target display data transmission rate for one or more displays, determine, by the differential analyzer, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate, transmit the one or more display data packets based on the actual display data transmission rate, and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. Other embodiments are described and claimed.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method, comprising: determining, by a processor circuit, a target display data transmission rate for one or more displays; generating, by a digital differential analyzer (DDA) communicatively coupled to the processor circuit, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate; transmitting the one or more display data packets based on the actual display data transmissio…
Assignees
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Classifications
- H04L9/40Primary
Electricity · mapped topic
- G06F3/1423Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9304731B2 cover?
- Techniques for rate governing of a display data stream are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module comprising a differential analyzer. In some embodiments, the graphics management module may be operative on the processor circuit to determine a target display data transmission rate for one or more displays, determi…
- Who is the assignee on this patent?
- Ansari Nausheen, Witter Todd M, Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H04L9/40. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).