Methods to achieve accurate time stamp in IEEE 1588 for system with FEC encoder

Patent metadata

Field	Value
Publication number	US-9300421-B2
Application number	US-201314058718-A
Country	US
Kind code	B2
Filing date	Oct 21, 2013
Priority date	Mar 14, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s) from forward error correction (FEC) sublayer changes in a data frame that is transmitted by the MAC layer. Feedback is provided to the MAC from the FEC to allow the MAC to accurately determine the timestamp point and timestamp value align preamble of the data frame to the beginning of the FEC bit block that is output by the FEC sublayer.

First claim

What is claimed is:

1. A communication system for an integrated circuit, the system comprising:
transmitter circuitry including:
a medium access control (MAC) layer; and
a forward error correction (FEC) layer coupled to the MAC layer by a data link and a feedback link, wherein the MAC layer is operable to send a message to the FEC layer on the data link, wherein the FEC layer asserts a feedback signal on the feedback link when the message arrives at the FEC layer, and wherein the MAC layer determines a timestamp value associated with the message based on the asserted feedback signal.

2. The system of claim 1 , wherein the message includes a preamble of an Ethernet frame.

3. The system of claim 1 , wherein the feedback signal is generated by a signal checking block within the FEC layer.

4. The system of claim 1 , wherein the transmitter circuitry includes a physical coding sub-layer (PCS) that includes a signal delay block, wherein the PCS is coupled between the MAC layer and the FEC layer, and wherein the feedback signal is based on an output of the signal delay block.

5. The system of claim 4 , wherein the PCS includes a pulse generation block, and wherein the feedback signal is based on an output of the pulse generation block.

6. The system of claim 4 , wherein the transmitter circuitry is IEEE 10G-BASE KR transmitter circuitry, and wherein the message includes a timestamp value as a part of a Precision Time Protocol message.

7. A method for determining a timestamp value using a communication system for an integrated circuit, the method comprising:
sending a message to a forward error correction (FEC) layer on a data link using a medium access control (MAC) layer;
asserting a feedback signal on a feedback link when the message arrives at the FEC layer using the FEC layer, wherein the FEC layer is coupled to the MAC layer by the data link and the feedback link, and wherein the FEC layer and the MAC layer are included in transmitter circuitry within the communication system; and
determining, using the MAC layer, the timestamp value associated with the message based on the asserted feedback signal.

8. The method of claim 7 , wherein the message includes a preamble of an Ethernet frame.

9. The method of claim 7 , further comprising generating the feedback signal using a signal checking block within the FEC layer.

10. The method of claim 7 , wherein a physical coding sub-layer (PCS), included in the transmitter circuitry, is coupled between the MAC layer and the FEC layer, and wherein the feedback signal is based on an output of a signal delay block within the PCS.

11. The method of claim 10 , wherein the feedback signal is based on an output of a pulse generation block within the PCS.

12. The method of claim 10 , wherein the transmitter circuitry is IEEE 10G-BASE KR transmitter circuitry, and wherein the message includes the timestamp value as a part of a Precision Time Protocol message.

13. A communication system for a programmable logic device, the system comprising:
a medium access control (MAC) layer; and
a forward error correction (FEC) layer coupled to the MAC layer by a feedback link, wherein the MAC layer is operable to send a message to the FEC layer,
wherein the FEC layer asserts a feedback signal on the feedback link when the message arrives at the FEC layer, and wherein the MAC layer determines a timestamp value associated with the message based on the asserted feedback signal.

14. The system of claim 13 , wherein the message includes a preamble of an Ethernet frame.

15. The system of claim 13 , wherein the feedback signal is generated by a signal checking block within the FEC layer.

16. The system of claim 13 further comprising a physical coding sub-layer (PCS) that includes a signal delay block, wherein the PCS is coupled between the MAC layer and the FEC layer, and wherein the feedback signal is based on an output of the signal delay block.

17. The system of claim 16 , wherein the PCS includes a pulse generation block, and wherein the feedback signal is based on an output of the pulse generation block.

Assignees

• Altera Corp

Inventors

• Yang Haiyun
• Mendel David W
• Duwel Keith
• Ngo Huy
• Schmit Herman Henry

Classifications

• H04J3/0667

  Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864) · CPC title

• H04J3/0697 Primary

  Synchronisation in a packet node · CPC title

• H04L1/0042

  Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence) · CPC title