Digitally controlled oscillator device and high frequency signal processing device

Patent metadata

Field	Value
Publication number	US-9300306-B2
Application number	US-201414513644-A
Country	US
Kind code	B2
Filing date	Oct 14, 2014
Priority date	Oct 13, 2011
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

First claim

What is claimed is:

1. A semiconductor device comprising:
a low noise amplifier configured to amplify a radio frequency signal inputted from an antenna;
a first reception mixer coupled with the low noise amplifier;
a reception digital PLL circuit including a first digitally controlled oscillator circuit; and
a reception divider coupled with the reception digital PLL circuit and the first reception mixer,
wherein the first digitally controlled oscillator circuit includes:
first and second oscillation output nodes from which complementary oscillation output signals are output;
coil elements coupled between the first oscillation output node and the second oscillation output node; and
a plurality of capacitor units coupled in parallel between the first oscillation output node and the second oscillation output node, and controlled through a plurality of control lines,
wherein a first shield layer is disposed between the control lines and the first and second oscillation output nodes in such a manner as to effectively shield between the control lines and the first and second oscillation output nodes.

2. A semiconductor device according to claim 1 ,
wherein the first digitally controlled oscillator circuit further includes a negative resistance generating circuit which generates a negative resistance between the first oscillation output node and the second oscillation output node, and a control circuit which controls the capacitor units through the control lines.

3. A semiconductor device according to claim 1 ,
wherein each of the capacitor units includes capacitive elements and a control node which is coupled to one of the control lines to select whether the capacitive elements are coupled to the first and second oscillation output nodes as set parameters for an oscillation frequency.

4. A semiconductor device according to claim 1 , further comprising:
a first programmable gain circuit coupled with the first reception mixer; and
a first low-pass filter coupled with the first programmable gain circuit.

5. A semiconductor device according to claim 4 , further comprising:
a second reception mixer coupled with the low noise amplifier;
a second programmable gain circuits coupled with the second reception mixer; and
a second low-pass filter coupled with the second programmable gain circuits.

6. A semiconductor device according to claim 1 , further comprising:
a variable driver configured to generate a transmission radio frequency signal;
a first transmission mixer coupled with the variable driver;
a transmission digital PLL circuit including a second digitally controlled oscillator circuit; and
a transmission divider coupled with the transmission digital PLL circuit and the first transmission mixer.

7. A semiconductor device according to claim 1 ,
wherein a part of the first shield layer is disposed so as to surround all the peripheries of the control lines over a section.

8. A semiconductor device according to claim 1 ,
wherein the control lines include first and second control lines,
wherein the first control line is coupled to the control nodes of 2 N (where N: integer equal to or greater than 0) capacitor units of the capacitor units,
wherein the second control line is coupled to the control nodes of 2 M (where M: integer equal to or greater than 0) capacitor units of the capacitor units,
wherein the control circuit includes a first buffer circuit which drives the first control line, and a second buffer circuit which drives the second control line, and
wherein a drive capacity of the second buffer circuit is 2 (M-N) times a drive capacity of the first buffer circuit.

Assignees

• Renesas Electronics Corp

Inventors

• Nakamura Takahiro

Classifications

• H03L7/1075 Primary

  by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence) · CPC title

• H03B5/1265 Primary

  switched capacitors · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L2207/12

  Indirect frequency synthesis using a mixer in the phase-locked loop · CPC title

• H03L2207/05

  Compensating for non-linear characteristics of the controlled oscillator · CPC title