Frequency synthesizer and related method for improving power efficiency

Patent metadata

Field	Value
Publication number	US-9300305-B1
Application number	US-201414557462-A
Country	US
Kind code	B1
Filing date	Dec 2, 2014
Priority date	Dec 2, 2014
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

First claim

What is claimed is:

1. A frequency synthesizer, comprising:
a digitally controlled oscillator (DCO), arranged to generate an oscillating clock;
a sigma-delta modulation (SDM) circuit, arranged to generate an SDM input to the DCO; and
a controller, arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

2. The frequency synthesizer of claim 1 , wherein the frequency synthesizer is implemented in an all-digital phase-locked loop (ADPLL).

3. The frequency synthesizer of claim 1 , wherein the controller is arranged to set the operating frequency of the SDM circuit to a first operating frequency when the transmit power level is within a first power level range, and to set the operating frequency of the SDM circuit to a second operating frequency when the transmit power level is within a second power level range.

4. The frequency synthesizer of claim 3 , wherein when a center power level of the first power level range is higher than a center power level of the second power level range, the first operating frequency is higher than the second operating frequency.

5. The frequency synthesizer of claim 3 , wherein the first power level range is not overlapped with the second power level range.

6. The frequency synthesizer of claim 1 , wherein a relationship between the operating frequency of the SDM circuit and the transmit power level is stored as a reference for the controller.

7. The frequency synthesizer of claim 1 , wherein the controller is arranged to adjust the operating frequency of the SDM circuit in response to the transmit power level by a step function.

8. The frequency synthesizer of claim 1 , wherein the operating frequency of the SDM circuit is derived from the oscillating clock, and the controller is arranged to change a divisor for adjusting the operating frequency of the SDM circuit.

9. The frequency synthesizer of claim 1 , wherein the controller is arranged to compare the transmit power level with a threshold to generate a comparison result, and sets the operating frequency of the SDM circuit according to the comparison result.

10. The frequency synthesizer of claim 9 , wherein the controller sets the operating frequency of the SDM circuit to a first operating frequency when the comparison result indicates that the transmit power level is larger than the threshold, and sets the operating frequency of the SDM circuit to a second operating frequency different from the first operating frequency when the comparison result indicates that the transmit power level is not larger than the threshold.

11. The frequency synthesizer of claim 10 , wherein the second operating frequency is lower than the first operating frequency.

12. The frequency synthesizer of claim 1 , wherein the controller is arranged to adjust the operating frequency of the SDM circuit with reference to at least one threshold of the transmit power level.

13. The frequency synthesizer of claim 12 , wherein the controller sets the at least one threshold according to at least a receive power level of a receiver.

14. The frequency synthesizer of claim 12 , wherein the controller sets the at least one threshold according to at least a sensitivity of a receiver.

15. The frequency synthesizer of claim 12 , wherein the controller sets the at least one threshold according to at least a signal-to-noise ratio (SNR) requirement of a receiver.

16. A frequency synthesizing method, comprising:
generating an oscillating clock based on a sigma-delta modulation (SDM) input from an SDM circuit of a frequency synthesizer; and
adjusting an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

17. The frequency synthesizing method of claim 16 , wherein the frequency synthesizer is implemented in an all-digital phase-locked loop (ADPLL).

18. The frequency synthesizing method of claim 16 , wherein the step of adjusting the operating frequency of the SDM circuit in response to the transmit power level of the transmitter using the oscillating clock comprises:
setting the operating frequency of the SDM circuit to a first operating frequency when the transmit power level is within a first power level range; and
setting the operating frequency of the SDM circuit to a second operating frequency when the transmit power level is within a second power level range.

19. The frequency synthesizing method of claim 18 , wherein when a center power level of the first power level range is higher than a center power level of the second power level range, the first operating frequency is higher than the second operating frequency.

20. The frequency synthesizing method of claim 16 , wherein the step of adjusting the operating frequency of the SDM circuit in response to the transmit power level of the transmitter using the oscillating clock comprises:
adjusting the operating frequency of the SDM circuit in response to the transmit power level by a step function.

Assignees

• Mediatek Inc

Inventors

• Kuo Chun-Ming
• Chen Chii-Horng
• Shen Shih-Chi

Classifications

• H03L7/0991 Primary

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title