Oscillator circuit, a semiconductor device and an apparatus

Patent metadata

Field	Value
Publication number	US-9300302-B2
Application number	US-201214395522-A
Country	US
Kind code	B2
Filing date	Apr 20, 2012
Priority date	Apr 20, 2012
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

An oscillator circuit for providing an output clock signal is described. The oscillator circuit comprising a voltage reference, a first current source, first capacitor, first capacitor switch, second current source, second capacitor, second capacitor switch, first comparator, second comparator and flip-flop. The first comparator comprises a first chopper-stabilized comparator switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in a first half-phase of the output clock signal to provide a first comparator output from comparing the first capacitor voltage to the reference voltage and in the zeroing phase in the second half-phase. The second comparator comprises a second chopper-stabilized comparator switchable between a respective compare phase and a respective zeroing phase in dependence on the output clock signal and arranged to operate in its compare phase in the second half-phase to obtain a second comparator output from comparing the second capacitor voltage to the reference voltage and in its zeroing phase in the first half-phase.

First claim

The invention claimed is:

1. An oscillator circuit for providing an output clock signal having an output frequency, the oscillator circuit comprising a voltage reference, a first current source, a first capacitor, a first capacitor switch, a second current source, a second capacitor, a second capacitor switch, a first comparator, a second comparator and a flip-flop,
the voltage reference arranged to carry a reference voltage,
the first capacitor arranged to, by operation of the first capacitor switch, be chargeable by the first current source to a first capacitor voltage on a first capacitor node in a first half-phase of the output clock and to be dischargeable in a second half-phase of the output clock;
the second capacitor arranged to, by operation of the second capacitor switch, be chargeable by the second current source to a second capacitor voltage on a second capacitor node in the second half-phase of the output clock and to be dischargeable in a first half-phase of the output clock;
the first comparator comprising a first chopper-stabilized comparator switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in the first half-phase to provide a first comparator output from comparing the first capacitor voltage to the reference voltage and arranged to operate in the zeroing phase in the second half-phase;
the second comparator comprising a second chopper-stabilized comparator switchable between a respective compare phase and a respective zeroing phase in dependence on the output clock signal and arranged to operate in its compare phase in the second half-phase to obtain a second comparator output from comparing the second capacitor voltage to the reference voltage and arranged to operate in its zeroing phase in the first half-phase phase;
the flip-flop being connected to the first comparator and the second comparator to receive the first comparator output and the second comparator output for generating the output clock signal and connected to the first comparator and the second comparator for providing the output clock signal to the first comparator and the second comparator;
a zeroing voltage reference arranged to carry a zeroing voltage, the inputs of each chopper-stabilized comparator being switchable to the zeroing voltage reference.

2. An oscillator circuit according to claim 1 , each of the first comparator and the second comparator comprising a respective delay unit for applying a delay to the respective comparator output before being provided to the flip-flop.

3. An oscillator circuit according to claim 1 , comprising:
a first comparator input switch arranged to provide the first chopper-stabilized comparator, during the first half-phase, with the first capacitor voltage and, during the second half-phase, with the reference voltage; and
a second comparator input switch arranged to provide the second chopper-stabilized comparator, during the second half-phase, with the second capacitor voltage and, during the first half-phase, with the reference voltage.

4. An oscillator circuit according to claim 3 , comprising:
a first reference voltage switch arranged to provide the first chopper-stabilized comparator, during the first half-phase, with the reference voltage from a first voltage reference line and, during the second half-phase, with the reference voltage from a second voltage reference line; and
a second reference voltage switch arranged to provide the second chopper-stabilized comparator, during the second half-phase, with the reference voltage from a third voltage reference line and, during the first half-phase, with the reference voltage from a fourth voltage reference line.

5. An oscillator circuit according to claim 1 , comprising:
first comparator input capacitors arranged at the inputs of the first chopper-stabilized comparator; and
second comparator input capacitors arranged at the inputs of the second chopper-stabilized comparator.

6. An oscillator circuit according to claim 1 , the zeroing voltage being different from the reference voltage.

7. An oscillator circuit according to claim 1 , the zeroing voltage being in a range of 50-100% of a supply voltage of the first comparator and the second comparator.

8. An oscillator circuit according to claim 1 , each chopper-stabilized comparator comprising a first amplifier stage and a second amplifier stage, the first amplifier stage comprising an amplifier for receiving differential input voltages and, in dependence on the differential input voltages, driving differential outputs to the second amplifier stage via intermediate coupling capacitors, the second stage arranged to provide the comparator output on its single-ended output.

9. An oscillator circuit according to claim 1 , each chopper-stabilized comparator comprising a plurality of zeroing switches arranged to connect the inputs of the first amplifier stage and the inputs of the second amplifier stage to the zeroing voltage reference during the zeroing phase.

10. An oscillator circuit according to claim 1 , the output frequency being in a range of 10 kHz-50 MHz.

11. A semiconductor device comprising an oscillator circuit according to claim 1 .

12. An apparatus comprising a semiconductor device according to claim 11 .

Assignees

• Bode Hubert
• Lesbats Mathieu
• Freescale Semiconductor Inc

Inventors

• Bode Hubert
• Lesbats Mathieu

Classifications

• H03L7/06 Primary

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H03K3/0231 Primary

  Astable circuits {(H03K3/0315 takes precedence)} · CPC title

• H03K4/50

  in which a sawtooth voltage is produced across a capacitor · CPC title