Antenna transmit receive switch

Patent metadata

Field	Value
Publication number	US-9300286-B2
Application number	US-201314040471-A
Country	US
Kind code	B2
Filing date	Sep 27, 2013
Priority date	Sep 27, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

An antenna switch is presented. The antenna switch can connect an antenna to either transmit circuitry or receive circuitry, depending on control signals applied to the antenna switch while presenting different impedances to a connected circuitry.

First claim

What is claimed is:

1. A circuital arrangement comprising:
a first port;
a second port;
a third port;
a first transistor arrangement;
a second transistor arrangement; and
a first reactive element,
wherein:
the circuital arrangement is configured to operate in one of a first mode and a second mode of operation, a mode of operation being determined by a control signal,
during the first mode of operation, the circuital arrangement is configured to present a first impedance at the first port and a second impedance at the second port and to provide a first electrical conduction path between the second port and the first port through the first transistor arrangement, while isolating the third port from the first electrical conduction path,
during the second mode of operation, the circuital arrangement is configured to present the first impedance at the first port and a third impedance different from the first impedance and the second impedance at the third port and provide a second electrical conduction path between the third port and the first port through the second transistor arrangement connected in series with the first reactive element, while isolating the second port from the second electrical conduction path, and
the first impedance and the second impedance are lower in value than the third impedance.

2. The circuital arrangement according to claim 1 , wherein the first electrical conduction path further comprises a second reactive element connected in series with the first transistor arrangement.

3. The circuital arrangement according to claim 2 , further comprising a control unit configured to generate the control signal.

4. The circuital arrangement according to claim 2 , wherein:
the first transistor arrangement comprises one or more first shunt transistor each connected to a corresponding one or more first series transistor and the second transistor arrangement comprises one or more second shunt transistor each connected to a corresponding one or more second series transistor, wherein:
during the first mode of operation, the one or more first series transistor and the one or more second shunt transistor are ON and the one or more first shunt transistor and the one or more second series transistor are OFF; and
during the second mode of operation, the one or more first series transistor and the one or more second shunt transistor are OFF and the one or more first shunt transistor and the one or more second series transistor are ON.

5. The circuital arrangement according to claim 4 wherein a port of a shunt transistor of the one or more first shunt transistor and/or the one or more second shunt transistor is connected to ground via a resistor.

6. The circuital arrangement according to claim 4 , wherein the transistors of the first and second transistor arrangements are MOSFETs.

7. The circuital arrangement according to claim 4 , wherein a transistor of the first and/or the second transistor arrangements is an accumulated charge control (ACC) silicon on insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET).

8. The circuital arrangement according to claim 4 , wherein a transistor of the first or the second transistor arrangements is a stacked transistor.

9. The circuital arrangement according to claim 8 , wherein a stack height of the stacked transistor is a function of an impedance value of the first impedance and/or the second impedance and/or the third impedance.

10. The circuital arrangement according to claim 9 , wherein the function is a ratio of impedance values.

11. The circuital arrangement according to claim 9 , wherein the stack height of a transistor of the first transistor arrangement is a ratio of a value of the first impedance and a value of the second impedance.

12. The circuital arrangement according to claim 9 , wherein the stack height of a transistor of the second transistor arrangement is a ratio of a value of the first impedance and a value of the third impedance.

13. The circuital arrangement according to claim 2 , wherein the first and/or the second reactive element comprises: a) an inductor with a fixed inductance, b) an inductor with a variable inductance, c) a capacitor with a fixed capacitance in series connection with a) or b), and d) a capacitor with a variable capacitance in series connection with a) or b).

14. The circuital arrangement according to claim 13 , wherein the variable inductor is a digitally tunable inductor (DTL) and/or the variable capacitor is a digitally tunable capacitor (DTC).

15. The circuital arrangement according to claim 2 , wherein the first and/or the second reactive element comprises a combination of series and/or shunt connected reactive elements.

16. The circuital arrangement according to claim 15 , wherein at least one reactive element of the combination of series and/or shunt connected reactive elements comprises a digitally tunable inductor (DTL) and/or a digitally tunable capacitor (DTC).

17. The circuital arrangement according to claim 2 , wherein the first impedance, the second impedance and the third impedance are determined by R ON and C OFF of the transistors from the first and second transistor arrangements in combination with the reactances of the first reactive element, the second reactive element and parasitic components associated with the circuital arrangement.

18. The circuital arrangement according to claim 17 , wherein the R ON and C OFF of the transistors from the first and second transistor arrangements are varied to achieve a desired first, second and third impedance.

19. The circuital arrangement according to 18 , wherein the R ON and C OFF are varied by changing sizes of the transistors from the first and second transistor arrangement.

20. The circuital arrangement according to claim 2 , wherein the values of the first impedance, the second impedance and the third impedance are varied by varying the sizes of the transistors from the first and second transistor arrangements in combination with a value of the first reactive element and the second reactive element.

21. The circuital arrangement according to claim 2 , wherein the first impedance is lower in value than the second impedance.

22. The circuital arrangement according to claim 1 or 2 , fabricated in the form of an integrated circuit.

23. The circuital arrangement according to claim 1 or 2 , fabricated entirely or partially using one of a) silicon on insulator (SOI) technology, and b) silicon on sapphire (SOS) technology.

24. The circuital arrangement according to claim 1 or 2 , further comprising:
a first impedance matching network;
a lowpass filter connected between the first impedance matching network and the second port;
a bandpass filter connected to the third port;
an antenna; and
a second impedance matching network connected between the first port and the antenna.

25. The circuital arrangement according to claim 24 , wherein the first impedance matching network is further connected to a transmit circuitry through a first power amplifier and the bandpass filter is further connected to a receive circuitry through a low noise amplifier.

26. The circuital arrangement according to claim 25 , wherein the first impedance matching network matches an impedance between the first power amplifier and the low pass filter and the second impedance matching network matches an impedance between the first port and the

Assignees

• Peregrine Semiconductor Corp

Inventors

• Gaynor Michael P
• Nobbe Dan William

Classifications

• H04B1/0458

  Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages (matching circuits in general H03H) · CPC title

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H04B1/18

  Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title

• H04B1/48

  in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter {(H04B1/46 takes precedence)} · CPC title