Method and apparatus for efficient load biasing

US9300261B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9300261-B2
Application numberUS-30820006-A
CountryUS
Kind codeB2
Filing dateMar 10, 2006
Priority dateMar 10, 2006
Publication dateMar 29, 2016
Grant dateMar 29, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A system for driving a plurality of loads each connected to respective signal terminals and to a shared common load terminal. Multiple conventional signal amplifiers each provide a content signal at one of the signal terminals. The signal amplifiers each have a primary-power upper terminal, to receive a first voltage (V 1 ) from a first power supply, and a primary-power lower terminal, to receive a second voltage (V 2 ) from the first power supply. A bias amplifier biases the common load terminal, and has a secondary-power upper terminal to receive a third voltage (V 3 ) from a second power supply and a secondary-power lower terminal to receive a fourth voltage (V 4 ) from the second power supply, wherein V 2 ≦V 4 <V 3 ≦V 1 .

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit for driving a plurality of loads, said circuit comprising: a first signal amplifier operable to supply a first content signal to a first terminal of a first load of said plurality of loads; a second signal amplifier operable to supply a second content signal to a second terminal of a second load of said plurality of loads, wherein said first and second signal amplifiers are configured to operate using a first voltage difference provided by a first power supply; and a bias amplifier operable to bias a third terminal of said first load and a fourth terminal of said second load with a bias signal of a bias voltage level, wherein said bias amplifier is configured to bias using a second voltage difference provided by a second power supply that is less than said first voltage difference, wherein said second voltage difference is close to said bias voltage level, wherein said second power supply includes at least one grounded terminal. 2. The circuit of claim 1 , wherein said bias amplifier is configured to operate using a first upper supply voltage provided by said second power supply , wherein said first and second amplifiers are configured to operate using a second upper supply voltage provided by said first power supply, and wherein said first upper supply voltage is less than said second upper supply voltage. 3. The circuit of claim 1 , wherein said bias amplifier is a Class-A amplifier. 4. The circuit of claim 1 , wherein said bias amplifier is a Class-AB amplifier. 5. The circuit of claim 1 , wherein said first and second amplifiers are selected from a group consisting of a plurality of Class-A amplifiers and a plurality of Class-AB amplifiers. 6. The circuit of claim 1 , wherein said plurality of loads are speakers. 7. A method of driving a plurality of loads, said method comprising: supplying a first content signal to a first load using a first signal amplifier, wherein said first signal amplifier is coupled to a first terminal of said first load; supplying a second content signal to a second load using a second signal amplifier, wherein said second signal amplifier is coupled to a second terminal of said second load, wherein said first and second signal amplifiers are configured to operate using a first voltage difference provided by a first power supply; and biasing, using a bias amplifier, a third terminal of said first load and a fourth terminal of said second load with a bias signal of a bias voltage level, wherein said bias amplifier is configured to bias using a second voltage difference provided by a second power supply that is less than said first voltage difference, wherein said second voltage difference is close to said bias voltage level, wherein said second power supply includes at least one grounded terminal. 8. The method of claim 7 , wherein said bias amplifier is configured to operate using a first upper supply voltage provided by said second power supply, wherein said first and second amplifiers are configured to operate using a second upper supply voltage provided by said first power supply, and wherein said first upper supply voltage is less than said second upper supply voltage. 9. The method of claim 7 , wherein said bias amplifier is a Class-A amplifier. 10. The method of claim 7 , wherein said bias amplifier is a Class-AB amplifier. 11. The method of claim 7 , wherein said first and second amplifiers are selected from a group consisting of a plurality of Class-A amplifiers and a plurality of Class-AB amplifiers. 12. The method of claim 7 , wherein said plurality of loads are speakers. 13. A system comprising: a first power supply; a second power supply; a first signal amplifier operable to supply a first content signal to a first terminal of a first load of said plurality of loads, wherein said first signal amplifier is powered by said first power supply; a second signal amplifier operable to supply a second content signal to a second terminal of a second load of said plurality of loads, wherein said second signal amplifier is powered by said first power supply, wherein said first and second signal amplifiers are configured to operate using a first voltage difference provided by said first power supply; and a bias amplifier operable to bias a third terminal of said first load and a fourth terminal of said second load with a bias signal of a bias voltage level, wherein said bias amplifier is powered by said second power supply, and wherein said bias amplifier is configured to bias using a second voltage difference provided by said second power supply that is less than said first voltage difference, wherein said second voltage difference is close to said bias voltage level, wherein said second power supply includes at least one grounded terminal. 14. The system of claim 13 , wherein said bias amplifier is configured to operate using a first upper supply voltage provided by said second power supply, wherein said first and second amplifiers are configured to operate using a second upper supply voltage provided by said first supply, and wherein said first upper supply voltage is less than said second upper supply voltage. 15. The system of claim 13 , wherein said bias amplifier is a Class-A amplifier. 16. The system of claim 13 , wherein said bias amplifier is a Class-AB amplifier. 17. The system of claim 13 , wherein said first and second amplifiers are selected from a group consisting of a plurality of Class-A amplifiers and a plurality of Class-AB amplifiers. 18. The system of claim 13 , wherein said plurality of loads are speakers. 19. The system of claim 13 , wherein said bias amplifier is powered exclusively by said second power supply.

Assignees

Inventors

Classifications

  • Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

  • Headphones for stereophonic communication {(details thereof, e.g. relating to batteries, cables or control elements H04R1/10)} · CPC title

  • H03F3/20Primary

    Power amplifiers, e.g. Class B amplifiers, Class C amplifiers (H03F3/26 - H03F3/30 take precedence) · CPC title

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What does patent US9300261B2 cover?
A system for driving a plurality of loads each connected to respective signal terminals and to a shared common load terminal. Multiple conventional signal amplifiers each provide a content signal at one of the signal terminals. The signal amplifiers each have a primary-power upper terminal, to receive a first voltage (V 1 ) from a first power supply, and a primary-power lower terminal, to recei…
Who is the assignee on this patent?
Delano Cary L, Chester William R, Nvidia Corp
What technology area does this patent fall under?
Primary CPC classification H03F3/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).