III nitride semiconductor substrate, epitaxial substrate, and semiconductor device

Patent metadata

Field	Value
Publication number	US-9299890-B2
Application number	US-201414579460-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Sep 30, 2009
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

In a semiconductor device 100 , it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×10 10 pieces/cm 2 to 2000×10 10 pieces/cm 2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 . By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 . Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 , and improve the crystal quality of the epitaxial layer 22 . Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.

First claim

The invention claimed is:

1. A group III nitride semiconductor substrate used in a semiconductor device, comprising a surface layer on a surface of the group III nitride semiconductor substrate, wherein
a content of carbon compound in the surface layer is 22 atomic percentage or less of carbon, and
a surface roughness of the surface layer is 5 nm or less on an RMS basis.

2. The group III nitride semiconductor substrate according to claim 1 , wherein an inclination angle of a normal axis of the surface with respect to a c-axis is 10° to 81°.

3. The group III nitride semiconductor substrate according to claim 1 , wherein a plane orientation of the surface is one of a {20-21} plane, a {10-11} plane, a {20-2-1} plane, a {10-1-1} plane, a {11-22} plane, a {22-43} plane, a {11-21} plane, a {11-2-2} plane, a {22-4-3} plane and a {11-2-1} plane.

4. The group III nitride semiconductor substrate according to claim 1 , wherein the surface layer contains 30×10 10 pieces/cm 2 to 2000×10 10 pieces/cm 2 of sulfur and 2 atomic percentage to 20 atomic percentage of oxygen.

5. The group III nitride semiconductor substrate according to claim 1 , wherein the surface layer contains 40×10 10 pieces/cm 2 to 1500×10 10 pieces/cm 2 of sulfur.

6. The group III nitride semiconductor substrate according to claim 1 , wherein the surface layer contains 3 atomic percentage to 16 atomic percentage of oxygen.

7. The group III nitride semiconductor substrate according to claim 1 , wherein the surface layer contains 120×10 10 pieces/cm 2 to 15000×10 10 pieces/cm 2 of chlorine.

8. The group III nitride semiconductor substrate according to claim 1 , wherein the surface layer contains 100×10 10 pieces/cm 2 to 12000×10 10 pieces/cm 2 of silicon.

9. The group III nitride semiconductor substrate according to claim 1 , wherein a content of copper compound in the surface layer is 150×10 10 pieces/cm 2 or lower of copper.

10. The group III nitride semiconductor substrate according to claim 1 , wherein a dislocation density of the surface layer is 1×10 6 pieces/cm 2 or lower.

Assignees

• Sumitomo Electric Industries

Inventors

• Ishibashi Keiji

Classifications

• C30B23/025 Primary

  characterised by the substrate · CPC title

• C30B25/186

  being specially pre-treated by, e.g. chemical or physical means · CPC title

• C30B29/403

  AIII-nitrides · CPC title

• H10P90/129

  by polishing · CPC title

• H10P90/126

  by chemical etching · CPC title