Insulating gate-type bipolar transistor

Patent metadata

Field	Value
Publication number	US-9299818-B2
Application number	US-201214395914-A
Country	US
Kind code	B2
Filing date	May 29, 2012
Priority date	May 29, 2012
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

An object of the present invention is to provide a trench gate type IGBT achieving both retention of withstand voltage and lowering of ON-state voltage and to provide a method for manufacturing the trench gate type IGBT. The IGBT according to the present invention is an SJ-RC-IGBT which includes a drift layer having super junction structure, and includes an IGBT area and an FWD area on the rear surface. In the IGBT according to the present invention, a first drift layer has an impurity concentration of 1×10 15 atms/cm 3 or higher and lower than 2×10 16 atms/cm 3 , and a thickness of 10 μm or larger and smaller than 50 μm; and that a buffer layer has an impurity concentration of 1×10 15 atms/cm 3 or higher and lower than 2×10 16 atms/cm 3 , and a thickness of 2 μm or larger and smaller than 15 μm.

First claim

The invention claimed is:

1. An insulating gate-type bipolar transistor comprising:
a first conductivity-type buffer layer;
a first drift layer provided on a first main surface of said buffer layer;
a first conductivity-type second drift layer provided on said first drift layer;
a second conductivity-type base layer provided on said second drift layer;
a first conductivity-type emitter layer selectively provided on the front surface of said base layer;
a gate electrode penetrating from the front surface of said emitter layer into said second drift layer to be embedded with an insulating gate film interposed between the gate electrode and the surroundings;
an emitter electrode having conductivity with said emitter layer;
a collector layer provided on a second main surface of said buffer layer; and
a collector electrode provided on said collector layer,
wherein
said first drift layer has a structure containing first conductivity-type first layers and second conductivity-type second layers repeated in the horizontal direction,
said collector layer has a structure containing second conductivity-type first collector layers and first conductivity-type second collector layers repeated in the horizontal direction,
said first drift layer has an impurity concentration of 1×10 15 atoms/cm 3 or higher and lower than 2×10 16 atoms/cm 3 , and a thickness of 10 μm or larger and smaller than 50 μm, and
said buffer layer has an impurity concentration of 1×10 15 atoms/cm 3 or higher and lower than 2×10 16 atoms/cm 3 , and a thickness of 2 μm or larger and smaller than 15 μm.

2. The insulating gate-type bipolar transistor according to claim 1 , wherein insulating layers are appropriately provided between said first layers and said second layers.

3. The insulating gate-type bipolar transistor according to claim 1 , further comprising
a first conductivity-type carrier accumulating layer having a higher impurity concentration than the impurity concentration of said second drift layer between said second drift layer and said base layer in a condition in contact with said base layer.

4. The insulating gate-type bipolar transistor according to claim 1 , wherein the repetition pitch of said collector layer is equal to or longer than 5 times longer than the repetition pitch of said first drift layer, and shorter than 20000 times longer than the repetition pitch of said first drift layer.

5. The insulating gate-type bipolar transistor according to claim 1 , wherein the width of said second conductivity-type collector layers is determined such that voltage drop of 0.5 V or higher and lower than 0.7 V is generated in said buffer layer between intermediate positions of said first collector layers and said second collector layers at the current density at the time of snapback peak voltage.

6. An insulating gate-type bipolar transistor comprising:
a first conductivity-type buffer layer;
a first drift layer provided on a first main surface of said buffer layer;
a first conductivity-type second drift layer provided on said first drift layer;
a second conductivity-type base layer provided on said second drift layer;
a first conductivity-type emitter layer selectively provided on the front surface of said base layer;
a gate electrode penetrating from the front surface of said emitter layer into said second drift layer to be embedded with an insulating gate film interposed between the gate electrode and the surroundings;
an emitter electrode having conductivity with said emitter layer;
a collector layer provided on a second main surface of said buffer layer; and
a collector electrode provided on said collector layer,
wherein
said first drift layer has a structure containing first conductivity-type first layers, insulating layers, and second conductivity-type second layers repeated in this order in the horizontal direction,
said collector layer has a structure containing second conductivity-type first collector layers and first conductivity-type second collector layers repeated in the horizontal direction,
said first layers and said second layers have an impurity concentration of 1×10 15 atoms/cm 3 or higher and lower than 2×10 16 atoms/cm 3 ,
said first drift layer has a thickness of 10 μm or larger and smaller than 50 μm, and
said buffer layer has an impurity concentration of 1×10 15 atoms/cm 3 or higher and lower than 2×10 16 atoms/cm 3 , and a thickness of 2 μm or larger and smaller than 15 μm.

7. The insulating gate-type bipolar transistor according to claim 6 , further comprising
a first conductivity-type carrier accumulating layer having a higher impurity concentration than the impurity concentration of said second drift layer between said second drift layer and said base layer in a condition in contact with said base layer.

8. The insulating gate-type bipolar transistor according to claim 6 , wherein the repetition pitch of said collector layer is equal to or longer than 5 times longer than the repetition pitch of said first drift layer, and shorter than 20000 times longer than the repetition pitch of said first drift layer.

9. The insulating gate-type bipolar transistor according to claim 6 , wherein the width of said second conductivity-type collector layers is determined such that voltage drop of 0.5 V or higher and lower than 0.7 V is generated in said buffer layer between intermediate positions of said first collector layers and said second collector layers at the current density at the time of snapback peak voltage.

Assignees

• Aono Shinji
• Minato Tadaharu
• Mitsubishi Electric Corp

Inventors

• Aono Shinji
• Minato Tadaharu

Classifications

• H10D30/721

  having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET  (TFTs having gate-to-body connection H10D30/6708) · CPC title

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title