Transistor and method of operating same

Patent metadata

Field	Value
Publication number	US-9299783-B2
Application number	US-201414521868-A
Country	US
Kind code	B2
Filing date	Oct 23, 2014
Priority date	Oct 23, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A transistor includes a channel forming layer on a substrate, a gate on the channel forming layer and including an electrochemically indifferent metal, a solid electrolyte layer between the channel forming layer and the gate, the solid electrolyte layer is formed as a stack structure with the gate on the channel forming layer, an active metal layer including an electrochemically active metal capable of enabling channel switching by using an oxidation-reduction reaction of the electrochemically active metal so that the active metal layer forms a metal channel in a channel region between the channel forming layer and the solid electrolyte layer, and a source and a drain electrically connected to the active metal layer.

First claim

What is claimed is:

1. A transistor comprising:
a channel forming layer on a substrate;
a gate on the channel forming layer, the gate including an electrochemically indifferent metal;
a solid electrolyte layer between the channel forming layer and the gate, the solid electrolyte layer is formed as a stack structure with the gate on the channel forming layer;
an active metal layer including an electrochemically active metal and capable of enabling channel switching by using an oxidation-reduction reaction of the electrochemically active metal so that the active metal layer forms a metal channel in a channel region between the channel forming layer and the solid electrolyte layer; and
a source and a drain electrically connected to the active metal layer.

2. The transistor of claim 1 , wherein the active metal layer includes,
a first portion corresponding to the channel region, the first portion is located in the channel region between the channel forming layer and the solid electrolyte layer during a gate on state, by diffusion of the active metal through the solid electrolyte layer according to a gate voltage applied to the gate, and
a second portion contacting the source and the drain.

3. The transistor of claim 2 , wherein the active metal layer is formed of an active metal including at least one of copper (Cu), silver (Ag), zinc (Zn), and nickel (Ni).

4. The transistor of claim 1 , wherein
a thickness of the channel forming layer inhibits the formation of a current path, and
the channel forming layer includes a metal for seating the active metal present in the channel region when a first gate voltage is applied to the gate.

5. The transistor of claim 4 , wherein the channel forming layer has a thickness of about 1 nm or less.

6. The transistor of claim 4 , wherein the metal of the channel forming layer is an inactive metal having a lower oxidizing power than the active metal of the active metal layer.

7. The transistor of claim 6 , wherein the channel forming layer comprises at least one of titanium (Ti) and W.

8. The transistor of claim 1 , wherein the active metal layer is formed of an active metal including at least one of Cu, Ag, Zn, and Ni.

9. The transistor of claim 1 , wherein the gate is formed of an inactive metal including at least one of tungsten (W), platinum (Pt), gold (Au), and Ni.

10. The transistor of claim 1 , wherein the solid electrolyte layer comprises one of a chalcogenide material, a chalcogenide material doped with an active metal, and an oxide having a solid electrolyte characteristic.

11. The transistor of claim 10 , wherein the chalcogenide material is at least one of germanium tellurium (GeTe), antimony tellurium (SbTe), germanium antimony tellurium (GeSbTe), germanium sulfide (GeS), and germanium selenium (GeSe).

12. The transistor of claim 10 , wherein the active metal doped in the chalcogenide material includes at least one of Cu, Ag, Zn, and Ni.

13. The transistor of claim 10 , wherein the oxide is one of a tungsten oxide (WO 3 ) and a silicon oxide (SiO 2 ).

14. The transistor of claim 1 , wherein the channel forming layer acts as an adhesive between the upper surface of the substrate and the active metal layer.

15. The transistor of claim 14 , wherein the channel forming layer comprises at least one of Ti and W.

16. The transistor of claim 1 , wherein the substrate is at least one of an inorganic substrate, an organic polymer substrate, a glass substrate, a flexible substrate having an electrical insulation property, and an undoped silicon substrate.

17. The transistor of claim 1 , further comprising:
an insulating material layer on an upper surface of the substrate, the insulating material layer including one of a silicon oxide (SiO 2 ) and an aluminum oxide (Al 2 O 3 ).

18. The transistor of claim 1 , wherein the active metal layer comprises Cu, the solid electrolyte layer comprises chalcogenide material, the gate comprises W, and the channel forming layer comprises Ti.

19. The transistor of claim 1 , wherein at least one of the active metal layer, the gate, and the solid electrolyte layer is formed by one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

20. A method of operating the transistor of claim 1 , the method comprising:
diffusing the active metal in a first portion of the active metal layer corresponding to a channel region through the solid electrolyte layer such that the first portion of the active metal layer is located between the channel forming layer and the solid electrolyte layer when a first gate voltage is applied to the gate and is located between the solid electrolyte layer and the gate when a second gate voltage is applied to the gate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Woo-Young
• Kim Ki-Hong
• Choi Sang-Jun
• Kim Young-Eal
• Park Seong-Yong

Classifications

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/721

  having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET  (TFTs having gate-to-body connection H10D30/6708) · CPC title

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title