Semiconductor device and method of making same

Patent metadata

Field	Value
Publication number	US-9299712-B2
Application number	US-201414576463-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Jul 18, 2007
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

First claim

What is claimed is:

1. A method of fabricating a semiconductor wafer to form a memory area and a logic area, the memory area comprising nonvolatile memory devices comprising floating gate transistors, the logic area comprising field effect transistors, the method comprising:
separating the semiconductor wafer into memory and logic areas;
forming a first gate dielectric region over the memory area;
forming a second gate dielectric region over the logic area;
depositing and patterning a conducting material, wherein the conducting material forms a gate electrode over the logic areas and a floating gate electrode over the memory areas;
doping to form source regions, drain regions, and channel regions; and
forming a metallization region over the floating gate electrode, wherein the metallization region capacitively couples a control gate node to the floating gate electrode of the floating gate transistors, wherein forming the metallization region comprises forming a first metal feature and a second metal feature embedded in an insulating dielectric region, wherein the first metal feature is electrically coupled to the floating gate electrode and the second metal feature is electrically coupled to the control gate node, wherein the floating gate electrode and the first metal feature form a portion of a floating gate and the second metal feature forms a portion of a control gate of one of the floating gate transistors, wherein the control gate and floating gate form an interlocking finger structure.

2. The method of claim 1 , further comprising forming vertically stacked metal layers connected by vias, wherein each metal layer has another first metal feature and another second metal feature.

3. The method of claim 1 , wherein the control gate is formed entirely in metal.

4. The method of claim 3 , wherein the floating gate electrode comprises polysilicon.

5. The method of claim 1 , wherein the floating gate transistor is a source side injection memory.

6. The method of claim 1 , wherein the floating gate transistor is configured to be erased through carrier tunneling from the first metal feature to the second metal feature.

7. The method of claim 1 , wherein the floating gate transistor is configured to be erased through carrier tunneling from the floating gate electrode to the source region.

8. A semiconductor device comprising:
an active region disposed in a semiconductor body;
a source region, a channel region and a drain region disposed in the active region, the source region being spaced from the drain region by the channel region;
a floating gate electrode overlying the channel region and separated therefrom by a dielectric layer;
a first metal layer overlying the active region, the metal layer including a first metal feature electrically contacting the floating gate electrode and a second metal feature coupled to a control gate node; and
additional levels of metal layers over the first metal layer, each level in the additional levels of metal layers comprising another first metal feature electrically coupled to the floating gate electrode and another second metal feature coupled to the control gate node, wherein the floating gate electrode and the first metal feature form a portion of a floating gate and the second metal feature forms a portion of a control gate of a non-volatile memory cell, and wherein the control gate and floating gate form an interlocking finger structure.

9. The semiconductor device of claim 8 , wherein the non-volatile memory cell is part of a flash EEPROM memory device.

10. The semiconductor device of claim 8 , wherein the non-volatile memory cell is part of a a EEPROM memory device.

11. The semiconductor device of claim 8 , wherein the non-volatile memory cell is part of a a split gate memory device.

12. The semiconductor device of claim 8 , wherein the non-volatile memory cell is part of a a source side injection memory device.

Assignees

• Infineon Technologies Ag

Inventors

• Tempel Georg
• Andersen Ernst-Otto
• Gratz Achim

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10D64/665

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671) · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title