Fin isolation in multi-gate field effect transistors
US-8987790-B2 · Mar 24, 2015 · US
Method of forming semiconductor fins and insulating fence fins on a same substrate
US9299705B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9299705-B2 |
| Application number | US-201414181781-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 17, 2014 |
| Priority date | Feb 17, 2014 |
| Publication date | Mar 29, 2016 |
| Grant date | Mar 29, 2016 |
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- Title
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Abstract
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A semiconductor structure may be formed by forming a first semiconductor fin and a second inactive semiconductor fin above a substrate; depositing a masking layer above the first semiconductor fin and the second semiconductor fin; etching a trench in the masking layer exposing the second semiconductor fin while the first semiconductor fin remains covered by the masking layer; removing the second semiconductor fin to form a fin recess beneath the trench; filling the fin recess with an insulating material to form an insulating fence fin; and removing the masking layer to expose the first semiconductor fin and the insulating fence fin. A third semiconductor fin separating the first semiconductor fin from the second semiconductor fin may also be formed prior to depositing the masking layer and covered by the masking layer. The first semiconductor fin may be a pFET fin and the third semiconductor fin may be an nFET fin.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method of forming a semiconductor structure, the method comprising: forming a first semiconductor fin and a second semiconductor fin above a substrate, wherein the second semiconductor fin comprises an inactive fin; depositing a masking layer above the first semiconductor fin and the second semiconductor fin; etching a trench in the masking layer exposing the second semiconductor fin while the first semiconductor fin remains covered by the maskin…
Assignees
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Classifications
- H10D84/853Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9299705B2 cover?
- A semiconductor structure may be formed by forming a first semiconductor fin and a second inactive semiconductor fin above a substrate; depositing a masking layer above the first semiconductor fin and the second semiconductor fin; etching a trench in the masking layer exposing the second semiconductor fin while the first semiconductor fin remains covered by the masking layer; removing the secon…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D84/853. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).