Tamper resistant electronic system utilizing acceptable tamper threshold count

Patent metadata

Field	Value
Publication number	US-9299451-B2
Application number	US-201213354657-A
Country	US
Kind code	B2
Filing date	Jan 20, 2012
Priority date	Jan 20, 2012
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A tamper resistant electronic device includes multiple eFuses that are individually blown in each instance the electronic device is tampered with. For example an eFuse is blown when the electronic device is subjected to a temperature that causes solder reflow. Since it is anticipated that the electronic device may be tampered with in an acceptable way and/or an acceptable number of instances, functionality of the electronic device is altered or disabled only after a threshold number of eFuses are blown. In certain implementations, the threshold number is the number of anticipated acceptable tamper events. Upon a tamper event an individual eFuse is blown. If the total number of blown eFuses is less than the threshold, a next eFuse is enabled so that it may be blown upon a next tamper event.

First claim

What is claimed is:

1. A tamper resistant electronic system comprising:
a thermoelectric device that converts thermal energy supplied from a heat source external to the tamper resistant electronic system to electrical energy to program one or more thermo electronic fuses (eFuses);
a thermo eFuse blow monitor that determines the number of programmed thermo eFuses; and
an eFuse system comprising one or more eFuse links, the eFuse system associated with the thermo eFuse blow monitor that is enabled if the number of programmed thermo eFuses exceeds a threshold, wherein the number of programmed thermo eFuses is indicative of whether the electronic system has been tampered with and is a threshold condition of programming one or more eFuse links.

2. The tamper resistant electronic system of claim 1 wherein an eFuse link within the eFuse system is programmed with electrical energy supplied by the tamper resistant electronic system power supply.

3. The tamper resistant electronic system of claim 2 wherein functionality of the tamper resistant electronic system is disabled if a threshold number of eFuse links within the eFuse system are programmed.

4. The tamper resistant electronic system of claim 2 wherein destruct functionality of the tamper resistant electronic system is enabled if a threshold number of eFuse links within the eFuse system are programmed.

5. The tamper resistant electronic system of claim 1 wherein the heat source external to the tamper resistant electronic system is a solder reflow oven and wherein the thermoelectric device utilizes a temperature differential between a temperature of the solder reflow oven and a temperature of the thermoelectric device to program the one or more thermo eFuses.

6. The tamper resistant electronic system of claim 1 wherein the thermoelectric device programs the thermo eFuse if the thermoelectric device is exposed to a temperature greater than or equal to a solder reflow temperature.

7. The tamper resistant electronic system of claim 6 wherein a sense circuit senses whether a thermo eFuse has been programmed during initialization of the tamper resistant electronic system.

8. A method for managing the programming an eFuse system within a tamper resistant electronic system comprising:
comparing a number of programmed thermo eFuses within a thermo eFuse system to a threshold, the thermo eFuses programmed by a thermoelectric device that converts thermal energy supplied from a heat source external to the tamper resistant electronic system to electrical energy;
if the number of programmed thermo eFuses is greater than the threshold, enabling programming of one or more eFuse links of the eFuse system;
wherein the number of programmed thermo eFuses is indicative of whether an electronic system has been tampered with and is a threshold condition of programming one or more eFuse links.

9. The method of claim 8 further comprising:
comparing the number of programmed thermo eFuses to a previous number of programmed thermo eFuses.

10. The method of claim 9 further comprising:
if the number of programmed thermo eFuses has increased relative to the previous number of programmed thermo eFuses, enabling programming of the one or more eFuse links of eFuse system.

11. The method of claim 8 further comprising:
disabling functionality of a tamper resistant electronic system by programming the one or more eFuse links of eFuse system.

12. The method of claim 8 further comprising:
enabling self destruct functionality of a tamper resistant electronic system by programming the one or more eFuse links of eFuse system.

13. The method of claim 8 wherein the one or more eFuse links of the eFuse system is programmed with electrical energy supplied by a tamper resistant electronic system power supply.

14. The method of claim 8 wherein the heat source external to the eFuse system is a solder reflow oven.

15. The method of claim 14 wherein the thermoelectric device utilizes a temperature differential between a temperature of the solder reflow oven and a temperature of the thermoelectric device to program the thermo eFuses.

16. The method of claim 14 further comprising:
programming, with the thermoelectric device, a particular thermo eFuse if the thermoelectric device is exposed to a temperature greater than or equal to a solder reflow temperature; and
sensing, with a sense circuit, whether the particular thermo eFuse has been programmed during initialization of a tamper resistant electronic system.

17. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising a tamper resistant electronic system, the tamper resistant electronic system comprising:
a thermoelectric device that converts thermal energy supplied from a heat source external to the tamper resistant electronic system to electrical energy to program one or more thermo electronic fuses (eFuses);
a thermo eFuse blow monitor that determines the number of programmed thermo eFuses; and
an eFuse system comprising one or more eFuse links, the eFuse system associated with the thermo eFuse blow monitor that is enabled if the number of programmed thermo eFuses exceeds a threshold, wherein the number of programmed thermo eFuses is indicative of whether an electronic system has been tampered with and is a threshold condition of programming one or more eFuse links.

18. The design structure of claim 17 , wherein the design structure comprises a netlist.

19. The design structure of claim 17 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

20. The design structure of claim 17 , wherein the heat source external to the tamper resistant electronic system is a solder reflow oven and wherein the thermoelectric device utilizes a temperature differential between a temperature of the solder reflow oven and a temperature of the thermoelectric device to program the one or more thermo eFuses.

Assignees

• Hebig Travis R
• Kuczynski Joseph
• Meyer Iii Robert E
• Nickel Steven R
• IBM

Inventors

• Hebig Travis R
• Kuczynski Joseph
• Meyer Iii Robert E
• Nickel Steven R

Classifications

• G11C17/16

  using electrically-fusible links · CPC title

• G06F2201/00

  Indexing scheme relating to error detection, to error correction, and to monitoring · CPC title

• H04W4/00

  Services specially adapted for wireless communication networks; Facilities therefor · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G06F2203/00

  Indexing scheme relating to G06F3/00 - G06F3/048 · CPC title