Display device

Patent metadata

Field	Value
Publication number	US-9299302-B2
Application number	US-201113581357-A
Country	US
Kind code	B2
Filing date	Apr 7, 2011
Priority date	Jun 1, 2010
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A normal display portion, in which image display is performed by typical active-matrix drive, and a memory display portion, in which image display is performed by memory drive are provided on a substrate which defines a liquid crystal panel. Each pixel in the memory display portion is shaped so as to include a curve or a side not parallel to either gate bus lines or source bus lines. A plurality of pixel memory units, each including a flip-flop, are provided so as to correspond to their respective pixels in the memory display portion. Display data is provided to the pixel memory unit that corresponds to the first stage of a shift register which is constituted by connecting the flip-flops in the plurality of pixel memory units in series.

First claim

The invention claimed is:

1. A display device for displaying an image by changing display states of pixels, comprising:
a first display portion including a plurality of video signal lines, a plurality of scanning signal lines crossing the video signal lines, and pixel electrodes arranged in a matrix so as to correspond to their respective intersections of the video signal lines and the scanning signal lines and also correspond to the pixels, in the first display portion a display state of a pixel corresponding to each pixel electrode changes on the basis of a video signal being applied, when the scanning signal line that passes through the intersection that corresponds to the each pixel electrode is selected, to the video signal line that passes through the intersection, and
a second display portion having pixel memory capable of holding at least one-bit data for each pixel, in the second display portion a display state of a pixel changes on the basis of the data held in the pixel memory, wherein,
the first display portion and the second display portion are formed on the same substrate,
the pixels included in the first display portion have a rectangular shape with two sides parallel to the scanning signal lines and two sides parallel to the video signal lines,
the pixels included in the second display portion have a shape including a curve or a side not parallel to either the scanning signal lines or the video signal lines,
the second display portion includes a shift register including m flip-flops being provided so as to respectively correspond to m pixels, where m is a positive integer, and
each of the m flip-flops includes:
a first latch portion to take in an input data signal and hold the input data signal as transfer data; and
a second latch portion to take in the transfer data, hold the transfer data as output data, and output an output signal on the basis of the output data;

the second display portion is formed on the substrate so as to enclose the first display portion;
the flip-flops are connected in series so as to sequentially transfer data based on the input data signal in accordance with clock pulses;
the second display portion includes voltage selection portions provided so as to correspond to their respective flip-flops, each of the voltage selection portions selecting a first voltage or a second voltage in accordance with a logic value of the output signal from each of the flip-flops;
the second display portion includes display element portions provided so as to correspond to their respective flip-flops, each of the display element portions reflecting the voltage selected by the voltage selection portion in the display state of the pixel that corresponds to each of the flip-flops;
the second display portion further includes a selection portion for selecting either the output signal of the flip-flop that corresponds to the m'th stage of the shift register or the input data signal on the basis of a predetermined instruction signal and providing the selected signal to the flip-flop that corresponds to the first stage of the shift register, and
after the transfer of the data based on the input data signal to the m flip-flops, the selection portion selects the output signal of the flip-flop that corresponds to the m'th stage of the shift register.

2. The display device according to claim 1 , wherein,
the second display portion includes, as the shift register, a shift register including sixty flip-flops being provided so as to respectively correspond to sixty pixels, and
the level of the input data signal is set to a first level once for a period equivalent to an interval between occurrences of the clock pulses and is set to a second level during other periods.

Assignees

• Washio Hajime
• Sharp Kk

Inventors

• Washio Hajime

Classifications

• G09G2300/0857

  Static memory circuit, e.g. flip-flop · CPC title

• G02F2001/133388

  Physics · mapped topic

• G09G3/2085

  Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G02F1/133388

  with constructional differences between the display region and the peripheral region · CPC title