Continuous in-memory accumulation of hardware performance counter data

Patent metadata

Field	Value
Publication number	US-9298651-B2
Application number	US-201313925760-A
Country	US
Kind code	B2
Filing date	Jun 24, 2013
Priority date	Jun 24, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

In-memory accumulation of hardware counts in a computer system is carried out by continuously sending count values from full-speed hardware counter units to a memory controller. A sending unit periodically samples performance data from the hardware counter units, and transmits count values to a bus interface for an interconnection bus which communicates with the memory controller. The memory controller responsively updates an accumulated count value stored in system memory using the current count value, e.g., incrementing the accumulated count value. A count value can be sent with a pointer to a memory location and an instruction on how the location is to be updated. The instruction may be an atomic read-modify-write operation, and the memory controller can include a dedicated arithmetic logic unit to carry out that operation. A data harvester can then be used to harvest accumulated count values by reading them from a table in system memory.

First claim

What is claimed is:

1. A method of accumulating a hardware count for an electronic system comprising:
maintaining at least one current count value for at least one counted event of a hardware component of the electronic system in a hardware counter unit;
sending the current count value to a memory controller which controls access to a system memory device of the electronic system; and
the memory controller responsively updating an accumulated count value stored in the system memory device of the electronic system using the current count value.

2. The method of claim 1 wherein said updating of the accumulated count value comprises incrementing the accumulated count value according to the current count value.

3. The method of claim 1 wherein the electronic system is a computer system and the hardware component is a processor core the computer system which processes program instructions residing in the system memory device.

4. The method of claim 1 wherein said sending is performed by a sending unit which periodically samples performance data from the hardware counter unit including the current count value and transmits the current count value to a bus interface for an interconnection bus which communicates with the memory controller.

5. The method of claim 1 wherein said sending includes providing a memory pointer to a location in the system memory device and an instruction on how the location is to be updated.

6. The method of claim 5 wherein the instruction is for an atomic read-modify-write operation.

7. The method of claim 6 wherein the memory controller includes a dedicated arithmetic logic unit, and the atomic read-modify-write operation is carried out using the dedicated arithmetic logic unit.

8. The method of claim 1 , further comprising harvesting the accumulated count value by reading the accumulated count value from the system memory device and providing it to a performance monitor.

9. An electronic system comprising:
a plurality of hardware components;
a system memory device;
at least one hardware counter unit which maintains at least one current count value for at least one current counted event of one of the hardware components; and
a memory controller which controls access to said system memory device, and receives the current count value and responsively updates an accumulated count value stored in said system memory device using the current count value.

10. The electronic system of claim 9 wherein said memory controller updates the accumulated count value by incrementing the accumulated count value according to the current count value.

11. The electronic system of claim 9 being a computer system, and wherein the hardware component is a processor core which processes program instructions residing in said system memory device.

12. The electronic system of claim 9 further comprising:
an interconnection bus which communicates with said memory controller;
a bus interface for said interconnection bus; and
a sending unit which periodically samples performance data from said hardware counter unit including the current count value and transmits the current count value to said bus interface.

13. The electronic system of claim 9 wherein said memory controller receives, with the current count value, a memory pointer to a location in said system memory device and an instruction on how the location is to be updated.

14. The electronic system of claim 13 wherein the instruction is for an atomic read-modify-write operation.

15. The electronic system of claim 14 wherein said memory controller includes a dedicated arithmetic logic unit, and the atomic read-modify-write operation is carried out using said dedicated arithmetic logic unit.

16. The electronic system of claim 9 further comprising a performance monitor which harvests the accumulated count value by reading the accumulated count value from the system memory device.

17. A data harvester application for an electronic device in the form of a computer program product comprising:
a non-transitory computer-readable storage medium; and
program instructions residing in said storage medium for reading performance data from a table in a system memory device of a computer system wherein the performance data includes at least one accumulated count value for at least one counted event of a hardware component of the computer system.

18. The data harvester application of claim 17 wherein said program instructions are adapted to read the performance data from a table having multiple table sectors, each table sector having a plurality of records sets pertaining to different filtered events, and each record set containing one or more accumulated count values.

19. The data harvester application of claim 17 wherein said program instructions further obtain entrance counts from record sets of the table, obtain exit counts from the same record sets a predefined measurement interval after obtaining the entrance counts, and calculate exit-to-entrance count deltas.

20. The data harvester application of claim 17 wherein the table includes a plurality of record sets, and said program instructions support asynchronous reading of the performance data by using a timestamp to indicate that a given record set has been completely posted to memory.

Assignees

• IBM

Inventors

• Heyrman Peter J
• Indukuru Venkat R
• Love Carl E
• Sawdey Aaron C
• Vitale Philip L

Classifications

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F11/3409

  for performance assessment · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title