Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

Patent metadata

Field	Value
Publication number	US-9298643-B2
Application number	US-201514728541-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Sep 28, 2010
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.

First claim

What is claimed is:

1. A method of data processing comprising the steps of:
temporarily storing in a plurality of first level cache lines data for manipulation by a central processing unit;
storing for each first level each cache line a tag indicating a valid and a dirty status of corresponding data;
temporarily storing in a plurality of second level cache lines data for manipulation by the central processing unit;
storing for the second level cache a set of shadow tags corresponding to the tags of the first level cache;
storing data in a second level memory directly addressable by the central processing unit;
transferring data including transferring data into the second level directly addressable memory;
determining from the shadow tags if the address of a data transfer into the second level directly addressable memory is cached in the first level cache;
if said address of said data transfer into the second level directly addressable memory is cached in the first level cache, determining from said shadow tags if said data is valid and dirty in the first level cache, and
if said address of said data transfer into the second level directly addressable memory is cached in the first level cache as valid and dirty, then transferring said data into a corresponding cache line in the first level cache and not into the second level directly addressable memory.

2. The method of data processing of claim 1 , further comprising the steps of:
if said address of said data transfer into the second level directly addressable memory is not cached in the first level cache, transferring said data into the second level directly addressable memory.

3. The method of data processing of claim 1 , further comprising the steps of:
if said address of said data transfer into the second level directly addressable memory is cached in the first level cache as valid and clean, then transferring said data both into a corresponding cache line in the first level cache and into the second level directly addressable memory.

4. The method of data processing of claim 1 , further comprising the step of:
if said address of said data transfer into the second level directly addressable memory is cached in the first level cache as invalid, then transferring said data into the second level directly addressable memory and not into a corresponding cache line in the first level cache.

Assignees

• Texas Instruments Inc

Inventors

• Tran Jonathan Son Hung
• Damodaran Raguram
• Chachad Abhijeet Ashok
• Zbiciak Joseph Raymond Michael

Classifications

• G06F2212/221

  Static RAM · CPC title

• G06F13/1605

  based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36) · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F13/18

  based on priority control (G06F13/1605 takes precedence) · CPC title

• H03K21/00

  Details of pulse counters or frequency dividers · CPC title