Cache line history tracking using an instruction address register file storing memory location identifier

Patent metadata

Field	Value
Publication number	US-9298619-B2
Application number	US-201314084121-A
Country	US
Kind code	B2
Filing date	Nov 19, 2013
Priority date	Jun 14, 2012
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

Embodiments relate to tracking cache lines. An aspect of embodiments includes performing an operation by a processor. Another aspect of embodiments includes fetching a cache line based on the operation. Yet another aspect of embodiments includes storing in an instruction address register file at least one of (i) an operation identifier identifying the operation and (ii) a memory location identifier identifying a level of memory from which the cache line is populated.

First claim

What is claimed is:

1. A computer system for tracking cache lines, the system comprising:
a processor, the processor comprising fetch request logic for retrieving items from memory, the system configured to perform a method comprising:
performing an instruction memory access operation, the processor executing program instructions associated with the memory access operation;
fetching a cache line from a memory hierarchy based on the performing the operation, the memory hierarchy comprising at least one cache and a main storage, wherein the cache line is stored at an address in an original level of the memory hierarchy prior to the performing the memory access operation; and
based on the performing the operation, storing in an instruction address register file, at an entry corresponding to the cache line, a memory location identifier identifying the original level of the memory hierarchy and identifiers of one or more of the program instructions associated with the memory access operation, wherein the memory location identifier is different than the address; and
providing access to contents of the instruction address register file for sampling subsequent to completion of the performing, fetching, and storing.

2. The computer system of claim 1 , wherein an identifier of a program instruction includes at least a portion of a memory address of the program instruction.

3. The computer system of claim 1 , wherein an identifier of a program instruction includes an operation identifier identifying the operation.

4. The computer system of claim 1 , the method further comprising:
storing a first occurrence identifier in the instruction address register file as a function of fetch initializing the register, the first occurrence identifier indicating that a cache line has not been previously tracked by a previous operation and reused for a current operation, wherein the first occurrence identifier is reset upon logic detecting that the instruction address register file has changed.

5. The computer system of claim 4 , the method further comprising:
maintaining the memory location identifier for the cache line that has not been previously tracked by a previous operation and reused for a current operation.

6. The computer system of claim 1 , wherein the memory location identifier identifies a level of cache.

7. The computer system of claim 1 , wherein the operation includes one of an instruction stream sequentially crossing a cache line boundary, a redirection to a cache line and a restart event branching to a cache line.

Assignees

• IBM

Inventors

• Collura Adam B
• Prasky Brian R

Classifications

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F11/3471

  Address tracing · CPC title

• G06F2201/885

  Monitoring specific for caches · CPC title

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F11/34

  Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation {; Recording or statistical evaluation of user activity, e.g. usability assessment} · CPC title