Method and apparatus for dynamically allocating memory address space between physical memories

Patent metadata

Field	Value
Publication number	US-9298600-B2
Application number	US-201313738709-A
Country	US
Kind code	B2
Filing date	Jan 10, 2013
Priority date	Jan 10, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other. After the system is fabricated, a pointer value set that corresponds to an address boundary between at least two physical memories of the fabricated system is set during boot time and/or during run time when the size of the physical memories are known. The technique provides a faster time-to-market for microprocessor-based systems by allowing, for example, Application Specific Integrated Circuits (ASICs) comprising microprocessor systems on-chip be manufactured prior to the final firmware and software being fully developed. Additionally, the subject matter disclosed herein permits changes in memory-space allocation for finalized ASIC designs.

First claim

What is claimed is:

1. A method, comprising:
allocating a memory address space for each of a plurality of physical memories in a microprocessor-based system, a size of at least one of the plurality of physical memories being unknown at a time the memory address space for the at least one of the plurality of physical memories is allocated and at least two of the allocated memory address spaces overlapping at least a portion of each other, in which the overlapping portion comprises a difference between an anticipated maximum size of one of the at least two overlapping allocated memory address spaces and an anticipated maximum size of another of the at least two overlapping allocated memory address spaces;
fabricating the system after the allocating; and then
setting a pointer value corresponding to an address boundary between at least two of the plurality of physical memories of the fabricated system, the size of the at least one of the plurality of physical memories being known at a time the pointer is set.

2. The method according to claim 1 , wherein setting the pointer comprises setting the pointer at a boot time of the system based on the size of the at least one physical memory being known at a time the pointer is set.

3. The method according to claim 2 , wherein setting the pointer further comprises setting the pointer during a run time of the system after the boot time of the system.

4. The method according to claim 1 , wherein setting the pointer comprises setting the pointer during a run time of the system after a boot time of the system.

5. The method according to claim 1 , wherein the plurality of physical memories comprises at least one Read Only Memory (ROM) and at least one Random Access Memory (RAM).

6. The method according to claim 1 , wherein the plurality of physical memories comprises at least one Read Only Memory (ROM) and a plurality of Random Access Memories (RAMs),
the method further comprising setting a second pointer corresponding to a RAM of the plurality of RAMs selected to be active.

7. The method according to claim 1 , wherein the system comprising a microprocessor-based Application Specific Integrated Circuit (ASIC).

8. The method according to claim 7 , wherein the ASIC is part of an information-handling system.

9. The method according to claim 8 , wherein the information-handling system comprises a touch-screen display.

10. The method according to claim 8 , wherein the information-handling system comprises a wireless link interface.

11. The method of claim 1 , wherein the pointer value further corresponds to an address within the overlapping portion.

12. A method, comprising:
defining a memory space for a system;
allocating a memory address space for each of a plurality of physical memories in the system, a size of at least one of the plurality of physical memories being unknown at a time the memory address space for the at least one of the plurality of physical memories is allocated and at least two of the allocated memory address spaces overlapping at least a portion of each other, the overlapping portion comprising a difference between an anticipated maximum size of one of the at least two overlapping allocated memory address spaces and an anticipated maximum size of another of the at least two overlapping allocated memory address spaces;
fabricating the system after the allocating; and then
setting a pointer value corresponding to an address boundary between at least two of the plurality of physical memories of the fabricated system, the size of the at least one of the plurality of physical memories being known at a time the pointer is set.

13. The method according to claim 12 , wherein setting the pointer comprises setting the pointer at a boot time of the system based on the size of the at least one physical memory being known at a time the pointer is set.

14. The method according to claim 13 , wherein setting the pointer further comprises setting the pointer during a run time of the system after the boot time of the system.

15. The method according to claim 12 , wherein setting the pointer comprises setting the pointer during a run time of the system after a boot time of the system.

16. The method according to claim 12 , wherein the plurality of physical memories comprises at least one Read Only Memory (ROM) and at least one Random Access Memory (RAM).

17. The method according to claim 12 , wherein the plurality of physical memories comprises at least one Read Only Memory (ROM) and a plurality of Random Access Memories (RAMs),
the method further comprising setting a second pointer corresponding to a RAM of the plurality of RAMs selected to be active.

18. The method according to claim 12 , wherein the system comprising a microprocessor-based Application Specific Integrated Circuit (ASIC).

19. The method according to claim 18 , wherein the ASIC is part of an information-handling system, the information-handling system comprising a touch-screen display.

20. The method of claim 12 , wherein the pointer value further corresponds to an address within the overlapping portion.

Assignees

• Avnera Corp

Inventors

• Bentz Ole
• Mays Robert
• Nepple Bruce
• Anderson James

Classifications

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G06F2212/1012

  Design facilitation · CPC title

• G06F12/0223 Primary

  User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title