Semiconductor device that detects abnormalities of watchdog timer circuits

Patent metadata

Field	Value
Publication number	US-9298530-B2
Application number	US-201414527946-A
Country	US
Kind code	B2
Filing date	Oct 30, 2014
Priority date	Jul 12, 2010
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A diagnosis circuit 1 monitors a watchdog timer 2 and supplies a diagnosis result signal 1 indicating whether a monitoring result is normal or not to a diagnosis circuit 2. A diagnosis circuit 3 monitors a watchdog timer 1 and supplies a diagnosis result signal 3 indicating whether a monitoring result is normal or not to the diagnosis circuit 2. The diagnosis circuit 2 determines that the diagnosis circuit 1 or the watchdog timer 2 is abnormal when the diagnosis result signal 1 does not have a value indicating normal. Further, the diagnosis circuit 2 determines that the diagnosis circuit 3 or the watchdog timer 1 is abnormal when the diagnosis result signal 3 does not have a value indicating normal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a central processing unit (CPU);
a first watchdog timer that monitors a runaway of the CPU;
a second watchdog timer that monitors the runaway of the CPU;
a first diagnosis circuit that monitors the first watchdog timer and generates a first diagnosis result signal; and
a second diagnosis circuit that monitors the second watchdog timer and generates a second diagnosis result signal,
wherein the first diagnosis circuit receives the second diagnosis result signal and the second diagnosis circuit receives the first diagnosis result signal, and wherein the first and second diagnosis circuits monitor each other by the first and second diagnosis result signals.

2. The semiconductor device according to claim 1 , wherein the first diagnosis result signal includes a first operation notification signal indicating that the first diagnosis circuit is normally operating, and the second diagnosis result signal includes a second operation notification signal indicating that the second diagnosis circuit is normally operating.

3. The semiconductor device according to claim 2 , wherein the first diagnosis circuit generates the first operation notification signal at a predetermined period and the second diagnosis circuit generates the second operation notification signal at a predetermined period.

4. The semiconductor device according to claim 2 , wherein when the first diagnosis circuit does not receive the second operation notification signal, the first diagnosis circuit determines that the second diagnosis circuit is in abnormal condition, and
wherein when the second diagnosis circuit does not receive the first operation notification signal, the second diagnosis circuit determines that the first diagnosis circuit is in abnormal condition.

5. The semiconductor device according to claim 1 , further comprising:
a third diagnosis circuit that monitors the first and second diagnosis circuits and generates a third diagnosis result signal,
wherein the third diagnosis circuit receives the first and second diagnosis result signals,
wherein the first diagnosis circuit further receives the third diagnosis result signal and the second diagnosis circuit further receives the third diagnosis result signal, and
wherein the first, second and third diagnosis circuit monitor each other by the first, second and third diagnosis result signals.

6. The semiconductor device according to claim 5 , wherein the third diagnosis result signal includes a third operation notification signal indicating that the third diagnosis circuit is normally operating.

7. The semiconductor device according to claim 6 , wherein the third diagnosis circuit generates the third operation notification signal at a predetermined period.

8. The semiconductor device according to claim 6 , wherein when the first diagnosis circuit does not receive the third operation notification signal, the first diagnosis circuit determines that the third diagnosis circuit is in abnormal condition.

Assignees

• Renesas Electronics Corp

Inventors

• Fuchigami Takashi

Classifications

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0757 Primary

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title