Double solder bumps on substrates for low temperature flip chip bonding

Patent metadata

Field	Value
Publication number	US-9295166-B2
Application number	US-201514663754-A
Country	US
Kind code	B2
Filing date	Mar 20, 2015
Priority date	Aug 30, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.

First claim

What is claimed is:

1. A method comprising:
obtaining a structure comprising:
a substrate including a plurality of recesses;
a plurality of electrically conductive contact pads within the recesses; and
a plurality of solder bumps, each solder bump including a first solder bump structure comprised of a first solder having a first melting point, the first solder bump structure adjoining one of the contact pads and extending above a top surface of the substrate, and a layer of second solder completely covering the first solder bump structure, the second solder having a lower melting point than the first solder;

contacting electrically conductive elements of an integrated circuit chip with the solder bumps;
causing reflow of the layers of second solder, the first solder bump structures remaining solid during reflow of the layers of second solder; and
causing the second solder to solidify such that the structure is attached to the integrated circuit chip;
further including filling a space between the integrated circuit chip and the substrate with underfill material.

2. A method comprising:
obtaining a structure comprising:
a substrate including a plurality of recesses;
a plurality of electrically conductive contact pads within the recesses; and
a plurality of solder bumps, each solder bump including a first solder bump structure comprised of a first solder having a first melting point, the first solder bump structure adjoining one of the contact pads and extending above a top surface of the substrate, and a layer of second solder completely covering the first solder bump structure, the second solder having a lower melting point than the first solder;

contacting electrically conductive elements of an integrated circuit chip with the solder bumps;
causing reflow of the layers of second solder, the first solder bump structures remaining solid during reflow of the layers of second solder; and
causing the second solder to solidify such that the structure is attached to the integrated circuit chip;
wherein the contact pads each have a given diameter, further including contacting the electrically conductive elements of the integrated circuit chip with the first solder bump structures and forming a stand-off height between the chip and substrate of more than half the given diameter of the contact pads upon contacting the electrically conductive elements of the integrated circuit chip with the first solder bump solder structures.

3. A method comprising:
obtaining a structure comprising:
a substrate including a plurality of recesses;
a plurality of electrically conductive contact pads within the recesses; and
a plurality of solder bumps, each solder bump including a first solder bump structure comprised of a first solder having a first melting point, the first solder bump structure adjoining one of the contact pads and extending above a top surface of the substrate, and a layer of second solder completely covering the first solder bump structure, the second solder having a lower melting point than the first solder;

contacting electrically conductive elements of an integrated circuit chip with the solder bumps;
causing reflow of the layers of second solder, the first solder bump structures remaining solid during reflow of the layers of second solder; and
causing the second solder to solidify such that the structure is attached to the integrated circuit chip;
wherein each of the first solder bump structures has a frustoconical portion extending above the top surface of the substrate.

4. The method of claim 3 , wherein each of the first solder bump structures includes a base portion having a top surface coplanar with the top surface of the substrate, the layer of second solder completely covering the frustoconical portion of each first solder bump structure and the top surface of the base portion of each first solder bump structure.

5. The method of claim 4 , wherein the contact pads each have a given diameter, further including contacting the electrically conductive elements of the integrated circuit chip with the first solder bump structures and forming a stand-off height between the chip and substrate of more than half the given diameter of the contact pads upon contacting the electrically conductive elements of the integrated circuit chip with the first solder bump structures.

6. A method comprising:
obtaining a structure comprising:
a substrate including a plurality of recesses;
a plurality of electrically conductive contact pads within the recesses; and
a plurality of solder bumps, each solder bump including a first solder bump structure comprised of a first solder having a first melting point, the first solder bump structure adjoining one of the contact pads and extending above a top surface of the substrate, and a layer of second solder completely covering the first solder bump structure, the second solder having a lower melting point than the first solder;

contacting electrically conductive elements of an integrated circuit chip with the solder bumps;
causing reflow of the layers of second solder, the first solder bump structures remaining solid during reflow of the layers of second solder; and
causing the second solder to solidify such that the structure is attached to the integrated circuit chip;
further including providing a plurality of second solder bumps on the integrated circuit chip, the second solder bumps comprising a portion of each of the electrically conductive elements and having a melting point higher than the layer of second solder, and further wherein the plurality of second solder bumps remain in a solid state during the step of causing reflow of the layers of second solder.

7. The method of claim 6 , further including filling a space between the integrated circuit chip and the substrate with underfill material.

8. The method of claim 7 , wherein each of the first solder bump structures has a frustoconical portion extending above the top surface of the substrate and a base portion having a top surface coplanar with the top surface of the substrate, the layer of second solder completely covering the frustoconical portion of each first solder bump structure and the top surface of the base portion of each first solder bump structure.

Assignees

• Globalfoundries Inc

Inventors

• Gruber Peter A
• Lauro Paul A
• Nah Jae-Woong

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/01208

  using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title