Image sensor including data transmission circuit having split bus segments

Patent metadata

Field	Value
Publication number	US-9294703-B2
Application number	US-201314095082-A
Country	US
Kind code	B2
Filing date	Dec 3, 2013
Priority date	Dec 3, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A data transmission circuit of an image sensor includes first to Kth bus segments, and first to Kth data regeneration circuits respectively connected to the first to Kth bus segments and the first to (K−1)th data regeneration circuits respectively connected to the second to Kth bus segments. Each of the first to Kth data regeneration circuits may be embodied as one of a buffer, a logic gate, and a synchronous circuit operating in response to a clock signal.

First claim

What is claimed is:

1. A data transmission circuit of an image sensor comprising:
first to Kth bus segments arranged in series; and
first to Kth data regeneration circuits arranged in series and respectively connected to the first to Kth bus segments, and the first to (K−1)th data regeneration circuits respectively connected to the second to Kth bus segments,
wherein each of the first to (K−1)th data regeneration circuits is configured to transmit data of a previous one of the first to Kth bus segments to a next one of the first to Kth bus segments in response to a control clock signal.

2. The data transmission circuit of claim 1 , wherein each of the first to Kth data regeneration circuits is one of a buffer and a logic gate.

3. The data transmission circuit of claim 1 , wherein each of the first to Kth data regeneration circuits is a synchronous circuit operating in response to a clock signal.

4. The data transmission circuit of claim 1 , wherein the Kth data regeneration circuit is configured to output data of the Kth bus segment of the first to Kth bus segments as serial data.

5. The data transmission circuit of claim 1 , further comprising:
first to Kth address transmission circuits respectively transmitting addresses related to data transmitted through the first to Kth bus segments, the first to Kth address transmission circuits connected to each other in series.

6. The data transmission circuit of claim 5 , wherein each of the first to Kth address transmission circuits is one of a buffer and a logic gate.

7. The data transmission circuit of claim 5 , wherein each of the first to Kth address transmission circuits is a synchronous circuit operating in response to a clock signal.

8. The data transmission circuit of claim 5 , wherein a transmission timing of the data and a transmission timing of the address are synchronized with each other.

9. The data transmission circuit of claim 1 , wherein each of the first to Kth data regeneration circuits transmits respective data of the first to Kth bus segments in one direction.

10. The data transmission circuit of claim 1 , wherein each of the plurality of data regeneration circuits bi-directionally transmits respective data of the first to Kth bus segments.

11. A portable electronic device comprising:
an image sensor including,
a pixel array,
an analog-to-digital converter circuit configured to convert an analog pixel signal output from the pixel array to a digital signal, and
a data transmission circuit configured to transmit data related to the digital signal,

the data transmission circuit having,
first to Kth bus segments arranged in series, and
first to Kth data regeneration circuits arranged in series and respectively connected to the first to Kth bus segments and the first to (K−1)th data regeneration circuits respectively connected to the second to Kth bus segments; and

a processor configured to control an operation of the image sensor,
wherein each of the first to (K−1)th data regeneration circuits is configured to transmit data of a previous one of the first to Kth bus segments to a next one of the first to Kth bus segments in response to a control clock signal.

12. The portable electronic device of claim 11 , wherein each of the first to Kth data regeneration circuits is one of a buffer, a logic gate, and a synchronous circuit operating in response to a clock signal.

13. The portable electronic device of claim 11 , further comprising:
first to Kth address transmission circuits respectively transmitting addresses related to data transmitted through the first to Kth bus segments, the first to Kth address transmission circuits connected to each other in series.

14. The portable electronic device of claim 11 , wherein data of the first to Kth bus segments are sequentially transmitted through the first to Kth data regeneration circuits.

15. The portable electronic device of claim 11 , wherein data of the first to Kth bus segments are sequentially transmitted through the first to Kth data regeneration circuits operating in response to a clock signal.

16. An image sensor comprising:
a pixel array;
an analog-to-digital converter configured to convert an analog pixel signal output from the pixel array to a digital signal; and
a data transmission circuit configured to transmit data related to the digital signal, the data transmission circuit including,
first to Kth bus segments arranged in series, and
first to Kth data regeneration circuits arranged in series and respectively connected to the first to Kth bus segments and the first to (K−1)th data regeneration circuits respectively connected to the second to Kth bus segments,

wherein each of the first to (K−1)th data regeneration circuits is configured to transmit data of a previous one of the first to Kth bus segments to a next one of the first to Kth bus segments in response to a control clock signal.

17. The image sensor of claim 16 , further comprising:
a digital processing unit configured to generate addresses and configured to process data serially output from the data transmission circuit.

18. The image sensor of claim 17 , further comprising:
an encoding converter between the digital processing unit and the data transmission circuit, the encoding converter configured to encode and convert a first format code into a second format code.

19. The image sensor of claim 18 , wherein the first format code is one of one-hot, binary code, gray code, and thermometer code, and the second format code is the other one of the one-hot, the binary code, the gray code, and the thermometer code.

20. The image sensor of claim 16 , wherein a sum of lengths of the first to Kth bus segments is smaller than a length of the pixel array in an arrangement direction of the first to Kth bus segments.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choo Kyo Jin
• Jin Eun Young

Classifications

• H04N25/767 Primary

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N5/378 Primary

  Electricity · mapped topic

• H04N5/3742

  Electricity · mapped topic