Cell fabric hardware acceleration

US9294569B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9294569-B2
Application numberUS-201414501156-A
CountryUS
Kind codeB2
Filing dateSep 30, 2014
Priority dateMar 15, 2013
Publication dateMar 22, 2016
Grant dateMar 22, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An aspect includes a method for providing direct communication between a server and a network switch in a cell-based fabric. A host channel adapter of a cell fabric hardware accelerator is configured to provide the server with direct access to memory within the network switch. A plurality of data packets having a fixed size is received at the host channel adapter from the server. The host channel adapter is coupled to a bus of the server. A direct transmission is performed from the cell fabric hardware accelerator to the memory within the network switch on an interconnect bus to write the data packets directly into the memory.

First claim

Opening claim text (preview).

What is claimed: 1. A method for providing direct communication between a server and a network switch in a cell-based fabric, the method comprising: configuring a host channel adapter of a cell fabric hardware accelerator to provide the server with direct access to memory within the network switch; receiving a plurality of data packets having a fixed size at the host channel adapter from the server, the host channel adapter coupled to a bus of the server; and performing a direct transmission from the cell fabric hardware accelerator to the memory within the network switch on an interconnect bus to write the data packets directly into the memory via a memory access port of the network switch using a remote direct memory access (RDMA) operation, the memory access port providing line buffering and format adjustment between the interconnect bus and the memory, and the memory access port is independent of network ports of the network switch that send packets to a plurality of other network switches using variable packet sizes. 2. The method of claim 1 , further comprising: configuring the memory within the network switch as a cache memory of the server. 3. The method of claim 1 , wherein configuring the host channel adapter of the cell fabric hardware accelerator to provide direct access to memory within the network switch further comprises registering the memory to inform the server that the memory is accessible using remote direct memory access operations. 4. The method of claim 1 , further comprising: interfacing adaption logic between the host channel adapter and memory interface logic, the memory interface logic comprising a link layer chip and a physical interface coupled to the interconnect bus. 5. The method of claim 4 , further comprising: tracking events associated with the link layer chip using an event queue control of the host channel adapter. 6. The method of claim 1 , further comprising: scheduling work operations at the host channel adapter for the memory within the network switch using a queue pair in the host channel adapter based on work requests from the server. 7. The method of claim 6 , further comprising: providing the server with one or more transaction completion notifications for the scheduled work operations at the host channel adapter using a completion queue control. 8. The method of claim 1 , wherein the network switch is part of an Ethernet network comprising the other network switches. 9. A computer program product for providing direct communication between a server and a network switch in a cell-based fabric, the computer program product comprising: a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: configuring a host channel adapter of a cell fabric hardware accelerator to provide the server with direct access to memory within the network switch; receiving a plurality of data packets having a fixed size at the host channel adapter from the server, the host channel adapter coupled to a bus of the server; and performing a direct transmission from the cell fabric hardware accelerator to the memory within the network switch on an interconnect bus to write the data packets directly into the memory via a memory access port of the network switch using a remote direct memory access (RDMA) operation, the memory access port providing line buffering and format adjustment between the interconnect bus and the memory, and the memory access port is independent of network ports of the network switch that send packets to a plurality of other network switches using variable packet sizes. 10. The computer program product of claim 9 , further comprising: configuring the memory within the network switch as a cache memory of the server. 11. The computer program product of claim 9 , wherein configuring the host channel adapter of the cell fabric hardware accelerator to provide direct access to memory within the network switch further comprises registering the memory to inform the server that the memory is accessible using remote direct memory access operations. 12. The computer program product of claim 9 , further comprising tracking events associated with a link layer chip using an event queue control of the host channel adapter. 13. The computer program product of claim 9 , further comprising: scheduling work operations at the host channel adapter for the memory within the network switch using a queue pair in the host channel adapter based on work requests from the server. 14. The computer program product of claim 13 , further comprising: providing the server with one or more transaction completion notifications for the scheduled work operations at the host channel adapter using a completion queue control.

Assignees

Inventors

Classifications

  • Transfer mode dependent, e.g. ATM · CPC title

  • Store and forward routing · CPC title

  • for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS] · CPC title

  • Electricity · mapped topic

  • for storage area networks · CPC title

Patent family

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9294569B2 cover?
An aspect includes a method for providing direct communication between a server and a network switch in a cell-based fabric. A host channel adapter of a cell fabric hardware accelerator is configured to provide the server with direct access to memory within the network switch. A plurality of data packets having a fixed size is received at the host channel adapter from the server. The host chann…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H04L67/1097. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).