Controller area network (CAN) worst-case message latency with priority inversion

Patent metadata

Field	Value
Publication number	US-9294412-B2
Application number	US-201314013941-A
Country	US
Kind code	B2
Filing date	Aug 29, 2013
Priority date	Aug 29, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

This application discloses determining a worst-case latency in a controller area network (CAN) for messages experiencing priority inversion within individual controllers. A system to determine the worst-case latency can include a memory system to store computer-executable instructions and a computing system, in response to execution of the computer-executable instructions, can identify that a controller area network (CAN) design includes a controller configured to sequence messages for transmission over a shared bus with at least one of the messages experiencing priority inversion. The computing system also can determine a delay for the controller to present a first message to the shared bus for transmission when the first message is ordered behind a second message having a lower priority than the first message. The delay may be a portion of the worst-case latency corresponding to the priority inversion.

First claim

The invention claimed is:

1. A method comprising:
receiving, by a computing device, parameters associated with a controller area network (CAN) having multiple controllers configured to transmit messages over a shared bus based, at least in part, on priorities associated with the messages, wherein the parameters are configured to identify that at least one of the controllers is configured to internally order a subset of the messages for presentation to the shared bus with priority inversion, and wherein the parameters identify each message available to be delivered over the shared bus, a frame period on the shared bus, a transmission time of a frame on the shared bus, and an offset between an initiation of message delivery and a start of the frame period; and
determining, by the computing device, a delay in delivery of a target message through the controller area network caused by the priority inversion based, at least in part, on the parameters.

2. The method of claim 1 , further comprising determining, by the computing device, a worst-case latency associated with the delivery of the target message through the controller area network based, at least in part, on the parameters, wherein the worst-case latency includes the delay in the delivery of the target message through the controller area network caused by the priority inversion.

3. The method of claim 2 , wherein determining the worst-case latency further comprising:
determining, by the computing device, a first time interval corresponding to a time taken to generate of the target message;
determining, by the computing device, a second time interval corresponding to a time taken for the target message to gain access to the shared bus;
determining, by the computing device, a third time interval corresponding to a time taken for the target message to transmit on the shared bus to a destination controller; and
determining, by the computing device, a fourth time interval corresponding to a time taken to process the target message and deliver the target message to a destination endpoint device.

4. The method of claim 3 , wherein determining the second time interval further comprising:
determining, by the computing device, a first elapsed time period spanning from generation of the target message to initial presentation of the target message to the shared bus, wherein the first elapsed time period includes the delay caused by the priority inversion during delivery of the target message through the controller area network; and
determining, by the computing device, a second elapsed time period associated with arbitration of the target message on the shared bus.

5. The method of claim 1 , wherein the priority inversion occurs when the target message is ordered behind one or more messages having lower priorities than the target message.

6. The method of claim 1 , wherein the parameters are configured to indicate internal ordering schemes that are implemented by the controllers, and wherein one or more of the internally ordering schemes allow for priority inversion.

7. A system comprising:
a memory system configured to store computer-executable instructions; and
a computing system, in response to execution of the computer-executable instructions, is configured to identify that a controller area network (CAN) design includes a controller configured to sequence messages for transmission over a shared bus, and to determine a worst-case latency associated with a delivery of a first message over the shared bus in the controller area network design, wherein the worst-case latency includes a first time to generate of the first message, a second time for the first message to gain access to the shared bus, which includes a delay for the controller to present the first message to the shared bus for transmission when the first message is ordered behind a second message having a lower priority than the first message, a third time for the first message to transmit over the shared bus, and a fourth time to deliver the first message from the shared bus to a destination endpoint device.

8. The system of claim 7 , wherein the second time for the first message to gain access to the shared bus includes a first period defined between generation of the first message to initial presentation of the first message to the shared bus, and a second period associated with arbitration of the first message on the shared bus, wherein the first period includes the delay for the controller to present the first message to the shared bus for transmission.

9. The system of claim 7 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to identify that the controller area network design includes the controller by reviewing parameters associated with the controller area network design, which indicate one or more controllers in the controller area network design are capable of sequencing messages with at least one of the messages experiencing priority inversion for transmission over the shared bus.

10. The system of claim 9 , wherein the parameters identify a controller type for each controller in the controller area network.

11. The system of claim 9 , wherein the parameters identify each message available to be delivered over the shared bus, a frame period on the shared bus, a transmission time of a frame on the shared bus, and an offset between an initiation of message delivery and a start of the frame period.

12. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
identifying a controller area network (CAN) design includes a controller configured to sequence messages for transmission over a shared bus; and
determining a worst-case latency associated with a delivery of the first message over the shared bus in the controller area network design, wherein the worst-case latency includes a first time to generate of the first message, a second time for the first message to gain access to the shared bus, which includes a delay for the controller to present the first message to the shared bus for transmission when the first message is ordered behind a second message having a lower priority than the first message, a third time for the first message to transmit over the shared bus, and a fourth time to deliver the first message from the shared bus to a destination endpoint device.

13. The apparatus of claim 12 , wherein determining the worst-case latency for the second time interval further comprising:
determining a first elapsed time period spanning from generation of the first message to initial presentation of the first message to the shared bus, wherein the first elapsed time period includes the delay for the controller to present the first message to the shared bus for transmission; and
determining a second elapsed time period associated with arbitration of the first message on the shared bus.

14. The apparatus of claim 12 , wherein identifying that the controller area network design includes the controller further comprising reviewing parameters associated with the controller area network design, which indicate one or more controllers in the controller area network design are capable of sequencing messages with at least one of the messages experiencing priority inversion for transmission over the shared bus.

15. The apparatus of claim 14 , wherein the parameters identify each message available to be delivered over the shared bus, a frame period on the shared bus, a transmission time of a frame on the shared bus, and an offset b

Assignees

• Mentor Graphics Corp

Inventors

• Horvath Istvan
• Matyas Zoltan

Classifications

• H04L2012/5613

  Bus (including DQDB) · CPC title

• H04L47/56

  implementing delay-aware scheduling · CPC title

• H04J3/1617

  carrying packets or ATM cells · CPC title

• H04L12/40032

  Details regarding a bus interface enhancer · CPC title

• H04L47/2458

  Modification of priorities while in transit · CPC title