Reverse current blocking comparator

Patent metadata

Field	Value
Publication number	US-9294080-B2
Application number	US-201414228614-A
Country	US
Kind code	B2
Filing date	Mar 28, 2014
Priority date	Apr 26, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

An apparatus comprises at least one transistor configured as analog switch, a well biasing circuit configured to provide a dynamic electrical bias to a bulk region of the at least one transistor, and a comparator circuit in electrical communication with the well biasing circuit and the transistor. The comparator circuit is configured to detect a first operating condition of the transistor and a second operating condition of the transistor. The well biasing circuit is configured to apply a first electrical bias to the bulk region of a transistor when the first operating condition is detected and apply a second electrical bias to the bulk region of the transistor when the second operating condition is detected, and wherein the comparator is configured to apply hysteresis to detection of the first and second operating conditions.

First claim

What is claimed is:

1. An apparatus comprising:
at least one transistor configured as an analog switch;
a well biasing circuit configured to provide a dynamic electrical bias to a bulk region of the at least one transistor; and
a comparator circuit in electrical communication with the well biasing circuit and the transistor, wherein the comparator circuit is configured to detect a first operating condition of the transistor and a second operating condition of the transistor,
wherein the well biasing circuit is configured to apply a first electrical bias to the bulk region of the transistor when the first operating condition is detected and apply a second electrical bias to the bulk region of the transistor when the second operating condition is detected, and wherein the comparator is configured to apply hysteresis to detection of the first and second operating conditions.

2. The apparatus of claim 1 , wherein the first operating condition includes a voltage at an input of the transistor being greater than a voltage at an output of the transistor and the second operating condition includes the voltage at the input of the transistor being less than the voltage at the output of the transistor.

3. The apparatus of claim 1 , wherein the well biasing circuit is configured to reduce the bias of a p-type well of the transistor by a difference between the voltage at the input of the transistor and the voltage at the output of the transistor when the first operating condition is detected, and to increase the bias of an n-type well of the transistor by the difference between the voltage at the output of the transistor and the voltage at the input of the transistor when the second operating condition is detected.

4. The apparatus of claim 1 , wherein the comparator circuit is configured to apply adjustable hysteresis to detection of the first and second operating conditions.

5. The apparatus of claim 4 , wherein the comparator includes a plurality of cross coupled devices attached to current mirrors, and wherein the hysteresis is adjustable by changing a ratio of sizes of transistors used in the current mirrors.

6. The apparatus of claim 5 , including a current reference for the current mirrors, wherein the at least one transistor, the well biasing circuit, the comparator circuit and the current reference are included in an IC, and wherein the current reference is active upon application of a non-zero voltage to an n-type well of the IC.

7. The apparatus of claim 1 , wherein the transistor is included in an analog switch circuit and the comparator circuit includes an output configured to indicate an operating condition of the analog switch.

8. The apparatus of claim 7 , including a control circuit configured to alter operation of the analog switch circuit according to the output of the comparator.

9. The apparatus of claim 7 , wherein the output of the comparator circuit indicates at least one of a direction of current through the transistor or a magnitude of the current through the transistor.

10. The apparatus of claim 1 , wherein the transistor is included in a pass gate circuit.

11. The apparatus of claim 1 , wherein the at least one transistor, the well biasing circuit, and the comparator circuit are included in a battery charging system.

12. The apparatus of claim 11 , wherein the battery-charging system is configured to provide charge to a battery for a cellular phone.

13. The apparatus of claim 1 , wherein the comparator circuit is configured to detect, as the first operating condition of the transistor, a voltage at an input to the transistor being greater than a voltage at an output of the transistor by less than a threshold voltage of the transistor, and to detect, as the second operating condition, the voltage at the output of the transistor being greater than the voltage at the input of the transistor by less than the threshold voltage of the transistor.

14. A method comprising:
applying a first electrical bias to a bulk region of a transistor when a first operating condition of the transistor is detected, wherein the transistor is configured as an analog switch; and
applying a second electrical bias to the bulk region of the transistor when a second operating condition of the transistor is detected, wherein changing between the first electrical bias and the second electrical bias includes applying hysteresis to a change from the first electrical bias to the second electrical bias when the second operating condition is detected and applying hysteresis to a change from the second electrical bias to the first electrical bias when the first operating condition is detected.

15. The method of claim 14 , wherein applying a first electrical bias to a bulk region of a transistor includes applying the first electrical bias to the transistor of an analog switch circuit when detecting that a voltage at an input of the analog switch is greater than a voltage at an output of the analog switch, and wherein applying a second electrical bias to the bulk region of a transistor includes applying the second electrical bias to the transistor of the analog switch circuit when detecting that the voltage at the input of the analog switch is less than the voltage at the output of the analog switch.

16. The method of claim 14 , wherein applying a first electrical bias to a bulk region of a transistor includes reducing the bias of a p-type well of the transistor by a difference between a voltage at the input of the transistor and the voltage at the output of the transistor, and wherein applying a second electrical bias to a bulk region of the transistor includes increasing the bias of an n-type well of the transistor by the difference between the voltage at the output of the transistor and the voltage at the input of the transistor when the second operating condition is detected.

17. The method of claim 14 , wherein applying hysteresis includes applying hysteresis that is symmetrical for the change when the second operating condition is detected and for the change when the first operating condition is detected.

18. The method of claim 14 , including indicating an operating condition of the transistor, and altering operation of an analog switch circuit that includes the transistor according to the indicated operating condition.

19. The method of claim 18 , wherein indicating the operation of the transistor includes indicating a direction of current through the transistor.

20. The method of claim 18 , wherein indicating the operation of the transistor includes indicating a magnitude of current through the transistor.

Assignees

• Fairchild Semiconductor

Inventors

• Daigle Tyler
• Stultz Julie Lynn

Classifications

• H02J7/62

  against overcurrent · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H02J7/0029

  Electricity · mapped topic

• H03K17/063 Primary

  in field-effect transistor switches · CPC title