CMOS based RF antenna switch

Patent metadata

Field	Value
Publication number	US-9294050-B2
Application number	US-201314034081-A
Country	US
Kind code	B2
Filing date	Sep 23, 2013
Priority date	Sep 23, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

First claim

What is claimed is:

1. A semiconductor antenna switch, comprising:
a first antenna port for coupling to a first antenna;
a second antenna port for coupling to a second antenna;
a transmit/receive switch port for coupling to either said first antenna or said second antenna in accordance with a respective first control signal and a second control signal;
a matching network coupled to said transmit/receive switch port;
a first transistor switch coupled in series between said first antenna port and said matching network;
a second transistor switch coupled in series between said second antenna port and said matching network;
a first impedance coupled between a bulk terminal of said first transistor switch to V ss ;
a second impedance coupled between a bulk terminal of said second transistor switch to V ss ;
a first control circuit operative to reverse bias drain and source terminals of said first transistor switch with respect to a gate terminal thereof when said first transistor switch is placed in an off state; and
a second control circuit operative to reverse bias drain and source terminals of said second transistor switch with respect to a gate terminal thereof when said second transistor switch is placed in an off state.

2. The semiconductor antenna switch according to claim 1 , further comprising an inductor in series between said first antenna port and said first switch.

3. The semiconductor antenna switch according to claim 2 , wherein said inductor comprises a bond wire.

4. The semiconductor antenna switch according to claim 1 , further comprising an inductor in series between said second antenna port and said second switch.

5. The semiconductor antenna switch according to claim 4 , wherein said inductor comprises a bond wire.

6. The semiconductor antenna switch according to claim 1 , wherein said first switch is rendered conductive and said second switch is rendered nonconductive thereby coupling said first antenna port to said transmit/receive port.

7. The semiconductor antenna switch according to claim 1 , wherein said first switch is rendered nonconductive and said second switch is rendered conductive thereby coupling said second antenna port to said transmit/receive port.

8. The semiconductor antenna switch according to claim 1 , wherein said matching network comprises one or more inductors.

9. The semiconductor antenna switch according to claim 8 , wherein said one or more inductors comprise one or more bond wires.

10. The semiconductor antenna switch according to claim 1 , wherein said first switch is disabled for application with a single antenna.

11. The semiconductor antenna switch according to claim 1 , further comprising:
a first dc blocking capacitor coupled in series between said first transistor switch and said first antenna port and a second dc blocking capacitor in series between said first transistor switch and said matching network; and
a third dc blocking capacitor coupled in series between said second transistor switch and said second antenna port and a fourth dc blocking capacitor in series between said second transistor switch and said matching network.

12. A semiconductor antenna switch, comprising:
a first antenna port for coupling to a first antenna;
a second antenna port for coupling to a second antenna;
a transmit/receive switch port for coupling said first antenna and said second antenna to an RX circuit and a TX circuit in accordance with a respective first control signal and a second control signal;
a first field effect transistor (FET) switch having bulk, source, drain and gate terminals, the drain terminal coupled to said first antenna port, the source terminal coupled to said transmit/receive switch port, the gate terminal operative to receive source drain and gate signals for controlling said first FET switch;
a second field effect transistor (FET) switch having bulk, source, drain and gate terminals, the drain terminal coupled to said second antenna port, the source terminal coupled to said transmit/receive switch port, the gate terminal operative to receive source, drain and gate signals for controlling said second FET switch;
a first impedance coupled between the bulk terminal of said first transistor switch to V ss ;
a second impedance coupled between the bulk terminal of said second transistor switch to V ss ;
a first control circuit operative to generate said source, drain and gate signals applied to said first FET switch, wherein the drain and source terminals of of said first FET switch are revere biased with respect to the gate terminal when the first FET switch is placed in an off state; and
a second control circuit operative to generate said source, drain and gate signals applied to said second FET switch, wherein the drain and source terminals of said second FET switch are revere biased with respect to the gate terminal when the second FET switch is placed in an off state.

13. The semiconductor antenna switch according to claim 12 , further comprising an inductor in series between said first antenna port and said first FET switch.

14. The semiconductor antenna switch according to claim 13 , wherein said inductor comprises a bond wire.

15. The semiconductor antenna switch according to claim 12 , further comprising an inductor in series between said second antenna port and said second FET switch.

16. The semiconductor antenna switch according to claim 15 , wherein said inductor comprises a bond wire.

17. The semiconductor antenna switch according to claim 12 , further comprising a matching network disposed between said transmit/receive port and the source terminals of said first FET switch and said second FET switch.

18. The semiconductor antenna switch according to claim 12 , wherein said first FET switch is rendered conductive and said second FET switch is rendered nonconductive thereby coupling said first antenna port to said transmit/receive port.

19. The semiconductor antenna switch according to claim 12 , wherein said first FET switch is rendered nonconductive and said second FET switch is rendered conductive thereby coupling said second antenna port to said transmit/receive port.

20. The semiconductor antenna switch according to claim 12 , wherein said matching network comprises one or more inductors.

21. The semiconductor antenna switch according to claim 20 , wherein said one or more inductors comprise one or more bond wires.

22. The semiconductor antenna switch according to claim 12 , wherein said first FET switch is disabled for application with a single antenna.

23. A method of antenna switching, the method comprising:
using a first transistor switch to couple in series a first antenna port and a transmit/receive switch port;
using a second transistor switch to couple in series a second antenna port and a transmit/receive switch port;
coupling a first impedance between a bulk terminal of said first transistor switch to V ss ;
coupling a second impedance between a bulk terminal of said second transistor switch to V ss ;
reverse biasing drain and source terminals of said first transistor switch with respect to a gate terminal thereof when said first transistor switch is placed in an off state; and
reverse biasing drain and source terminals of said second transistor switch with respect to a gate terminal thereof when said second transistor switch is placed in an off state.

Assignees

• Dsp Group Ltd
• Dsp Group Ltd

Inventors

• Mostov Alexander
• Hasson Yaron

Classifications

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W44/241

  for passive devices or passive elements · CPC title

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/206

  Wires · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title