Current mode PWM boost converter with frequency dithering

Patent metadata

Field	Value
Publication number	US-9293988-B2
Application number	US-201314086256-A
Country	US
Kind code	B2
Filing date	Nov 21, 2013
Priority date	Dec 11, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A current mode PWM converter configured to maintain a duty ratio of a driving signal for driving a boost circuit boosting an input voltage to an output voltage when a frequency of a clock signal for generating the driving signal is varied.

First claim

What is claimed is:

1. A current mode pulse width modulation (PWM) converter, comprising:
a boost circuit configured to receive an input voltage, and boost the input voltage to an output voltage, the boost circuit comprising an inductor and a switch configured to control flow of a current flowing through the inductor;
a pseudo random clock generating unit configured to generate a clock signal, and vary a frequency of the clock signal;
a voltage divider configured to receive the output voltage, and divide the output voltage to a division voltage;
a reset signal generating circuit configured to generate a reset signal based on the division voltage and the current flowing through the boost inductor; and
a driving signal generating circuit configured to receive the clock signal and the reset signal, and generate a driving signal of the switch based on the clock signal and the reset signal, the driving signal having a low-to-high transition corresponding to a low-to-high transition of the clock signal and having a high-to-low transition corresponding to a low-to-high transition of the reset signal,
wherein in response to the pseudo random clock generating unit varying the frequency of the clock signal from a first frequency of the clock signal to a second frequency of the clock signal, the reset signal generating circuit controls activation time of the reset signal by varying a frequency of the reset signal in direct correlation to the pseudo random clock generating unit varying the frequency of the clock signal from the first frequency of the clock signal to the second frequency of the clock signal such that a duty ratio of the driving signal based on the first frequency of the clock signal is substantially equal to a duty ratio of the driving signal based on the second frequency of the clock signal, and
wherein the activation time of the reset signal is reduced in direct correlation to the pseudo random clock generating unit varying the frequency of the dock signal from the first frequency of the clock signal to the second frequency of the clock signal if the frequency of the clock signal decreases from a high frequency to a low frequency and the activation time of the reset signal is increased in direct correlation to the pseudo random clock generating unit varying the frequency of the clock signal from the first frequency of the clock signal to the second frequency of the clock signal if the frequency of the clock signal increases from a low frequency to a high frequency.

2. The current mode PWM converter of claim 1 , wherein the reset signal generating circuit comprises:
an error amplifier configured to compare the division voltage and a reference voltage, and to generate an error signal based on a result of comparing the division voltage and the reference voltage;
a feedback signal generating circuit configured to add a slope compensation ramp signal and a sensing signal obtained through sensing of the current flowing through the inductor to generate a feedback signal based on a result of adding the slope compensation ramps signal and the sensing signal; and
a comparator configured to compare the error signal and the feedback signal, and to output the reset signal based on a result of comparing the error signal and the feedback signal,
wherein a slope of the slope compensation ramp signal varies according to variation of the frequency of the clock signal.

3. The current mode PWM converter of claim 2 , wherein the feedback signal generating circuit decreases the slope of the slope compensation ramp signal if the frequency of the clock signal decreases from a high frequency to a low frequency and increases the slope of the slope compensation ramp signal if the frequency of the clock signal increases from a low frequency to a high frequency.

4. The current mode PWM converter of claim 3 , wherein the feedback signal generating circuit comprises:
an inductor current generating unit configured to sense the current flowing through the inductor, and to output the sensing signal based on the current flowing through the inductor;
a slope compensation ramp generating unit configured to generate the slope compensation ramp signal based on the clock signal, and vary the slope of the slope compensation ramp signal according to the variation of the frequency of the clock signal; and
an adder configured to add the sensing signal and the slope compensation ramp signal, and to generate the feedback signal based on a result of adding sensing signal and the slope compensation ramp signal.

5. The current mode PWM converter of claim 4 , wherein the clock generating unit comprises:
a pseudo random code generator configured to generate a pseudo random code; and
a clock generator configured to generate the pseudo random clock signal having a frequency varied according to the pseudo random code generated by the pseudo random code generator.

6. The current mode PWM converter of claim 5 , wherein the slope compensation ramp generating unit varies the slope of the slope compensation ramp signal according to the random code upon which the frequency of the clock signal is varied.

7. The current mode PWM converter of claim 1 , wherein the reset signal generating circuit comprises:
a feedback signal generating circuit configured to add a slope compensation ramp signal and a sensing signal obtained through sensing of the current flowing through the inductor, and to generate a feedback signal based a result of adding the slope compensation ramp signal and the sensing signal;
an error amplifier configured to compare the division voltage and a reference voltage, and to generate an error signal based on a result of comparing the division voltage and the reference voltage;
an error signal compensation circuit configured to vary a voltage level of the error signal according to variation of the frequency of the clock signal, to generate a compensation error signal; and
a comparator configured to compare the compensation error signal and the feedback signal, and to output the reset signal based on a result of comparing the compensation error signal and the feedback signal.

8. The current mode PWM converter of claim 7 , wherein the feedback signal generating circuit comprises:
an inductor current generating unit configured to sense the current flowing through the inductor, and to output the sensing signal based on the current flowing through the inductor;
a slope compensation ramp generating unit configured to generate the slope compensation ramp signal based on to the clock signal; and
an adder configured to add the sensing signal and the slope compensation ramp signal, and to generate the feedback signal based on a result of adding sensing signal and the slope compensation ramp signal.

9. The current mode PWM converter of claim 8 , wherein the error signal compensation circuit increases the voltage level of the error signal if the frequency of the clock signal is decreased from a high frequency to a low frequency and decreases the voltage level of the error signal if the frequency of the clock signal is increased from a low frequency to a high frequency.

10. A current mode PWM converter, comprising:
a boost circuit configured to receive an input voltage, and boost the input voltage to an output voltage, the boost circuit comprising an inductor and a switch configured to control flow of a current flowing through the inductor;
a voltage divider configured to receive the output voltage, and divide the output voltage to a division voltage;
an error amplifier configured to compare the division voltage and a reference voltage, and to generate an error signal based on a result of comparing the division voltage and the reference voltage;
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Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kyoungjin
• Oh Hyoungseok
• Yoon Jehyung

Classifications

• H02M3/157

  with digital control · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M2001/0025

  Electricity · mapped topic

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title