Reducing kickback current to power supply during charge pump mode transitions

Patent metadata

Field	Value
Publication number	US-9293986-B2
Application number	US-201314108101-A
Country	US
Kind code	B2
Filing date	Dec 16, 2013
Priority date	May 17, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Kickback current from a charge pump to a power management integrated circuit (PMIC) may be reduced by dissipating charge from fly and hold capacitors during mode transitions. A switch may be placed in series between the charge pump and the PMIC to disconnect the charge pump and prevent kickback current from reaching the PMIC. Further, additional loads, as switches, may be coupled to the charge pump outputs to dissipate charge from the fly and hold capacitors. Additionally, a closed feedback loop may be used to monitor and discharge excess charge from the fly and hold capacitors during mode transitions. Furthermore, charge may be redistributed between the fly and hold capacitors during mode transitions to reduce the time period of the transition.

First claim

What is claimed is:

1. An apparatus, comprising:
a charge pump comprising a first charge pump output node;
a charge pump voltage controller coupled to a voltage input of the charge pump and coupled to a supply voltage input node, wherein the charge pump voltage controller is configured to control an input voltage level to the voltage input of the charge pump by regulating a supply voltage received at the supply voltage input node;
an input switch coupled between the charge pump voltage controller and the voltage input of the charge pump; and
an amplifier controller configured to transition the charge pump from a higher voltage mode to a lower voltage mode and configured to provide a high impedance path during a transition period between the higher voltage mode and the lower voltage mode.

2. The apparatus of claim 1 , wherein the input switch comprises at least one of a switch and a buffer, wherein the input switch is configured to create at least a high impedance path and a low impedance path between the charge pump voltage controller and the charge pump.

3. The apparatus of claim 1 , wherein the amplifier controller is configured to transition the charge pump from the higher voltage mode to the lower voltage mode to adapt to at least one of an input signal and a volume level of the amplifier.

4. The apparatus of claim 1 , wherein the charge pump further comprises a second charge pump output node.

5. The apparatus of claim 4 , further comprising:
a first capacitor coupled to the first charge pump output node and to a ground;
a second capacitor coupled to the second charge pump output node and to the ground; and
a load coupled to the first charge pump output node and the second charge pump output node, wherein the load is configured to drain at least one of the first capacitor and the second capacitor during at least a portion of time during the transition from the higher voltage mode to the lower voltage mode.

6. The apparatus of claim 5 , further comprising:
a first switch coupled to the first charge pump output node and to a ground; and
a second switch coupled to the second charge pump output node and to the ground.

7. The apparatus of claim 6 , wherein the amplifier controller is configured to control the first switch and the second switch to discharge the first capacitor and the second capacitor, respectively, during at least a portion of the transition between the higher voltage mode and the lower voltage mode.

8. The apparatus of claim 6 , wherein the amplifier controller is configured to redistribute charge between the first capacitor and the second capacitor.

9. The apparatus of claim 5 , further comprising:
a third capacitor coupled to the first charge pump output node; and
a fourth capacitor coupled to the second charge pump output node,
a first switch coupled between the third capacitor and the first charge pump output node;
a second switch coupled between the third capacitor, the fourth capacitor, and the ground; and
a third switch coupled between the fourth capacitor and the second charge pump output node.

10. The apparatus of claim 9 , wherein the amplifier controller is configured to perform the following steps during at least a portion of the transition of the charge pump from the higher voltage mode to the lower voltage mode:
configure the input switch to provide a high impedance path to reduce kickback current to the voltage controller; and
switch on the first switch, the second switch, and the third switch to drain charge from the third capacitor and the fourth capacitor by coupling the third capacitor and the fourth capacitor to the first capacitor and the second capacitor, respectively, to discharge the third capacitor and the fourth capacitor in parallel with the first capacitor and the second capacitor.

11. The apparatus of claim 4 , further comprising:
a first capacitor coupled to the first charge pump output node and a ground;
a second capacitor coupled to the second charge pump output node and the ground;
a first comparator comprising a first input coupled to a signal proportional to the first charge pump output node and a second input coupled to a first reference voltage; and
a second comparator comprising a first input coupled to a signal proportional to the second charge pump output node and a second input coupled to a second reference voltage.

12. The apparatus of claim 11 , further comprising:
a third capacitor coupled to the first charge pump output node and a common node;
a fourth capacitor coupled to the second charge pump output node and the common node;
a first switch coupled between the third capacitor and the first charge pump output node;
a second switch coupled between the common node and the ground; and
a third switch coupled between the fourth capacitor and the second charge pump output node.

13. The apparatus of claim 12 , wherein the amplifier controller is configured to perform the following steps during a transition of the charge pump from high voltage mode to a low voltage mode:
configure the input switch to provide a high impedance path to reduce kickback current to the voltage controller; and
switch on the first switch, the second switch, and the third switch to drain charge from the third capacitor and the fourth capacitor by coupling the third capacitor and the fourth capacitor to the first capacitor and the second capacitor, respectively, to discharge the third capacitor and the fourth capacitor in parallel with the first capacitor and the second capacitor.

14. The apparatus of claim 12 , further comprising logic circuitry coupled to the first comparator and coupled to the second comparator and coupled to the charge pump, wherein the logic circuitry is configured to monitor the first charge pump output node and the second charge pump output node and generate a trip signal when at least one of the first comparator and the second comparator indicate at least one of the first charge pump output node and the second charge pump output node have discharged to approximately a voltage value for operation in the low voltage mode.

15. The apparatus of claim 14 , wherein the amplifier controller is configured to perform the following steps when the trip signal is generated:
configure the input switch to provide a high impedance path to reduce kickback current to the voltage controller; and
switch off the first switch, the second switch, and the third switch to drain charge from the third capacitor and the fourth capacitor by coupling the third capacitor and the fourth capacitor to the first capacitor and the second capacitor, respectively, to discharge the third capacitor and the fourth capacitor in parallel with the first capacitor and the second capacitor.

16. The apparatus of claim 14 , wherein the amplifier controller is configured to redistribute charge between the first capacitor and the second capacitor.

17. The apparatus of claim 16 , wherein the fourth capacitor is configured to redistribute charge with the first capacitor in a first phase, and the fourth capacitor is configured to redistribute charge with the second capacitor in a different second phase, until voltages on the first capacitor and the second capacitor have discharged to approximately the lower voltage mode.

18. The apparatus of claim 14 , further comprising:
a fourth switch coupled to the common node and coupled to the first charge pump output node; and
a fifth switch coupled to the second capacitor and coupled to the ground.

19. The apparatus of claim 18 , wherein the amplifier

Assignees

• Cirrus Logic Inc

Inventors

• Thandri Bharath Kumar
• Nguyen Thuan L
• Allen Daniel John
• Zhang Lingli
• Satoskar Aniruddha
• Brennan Aaron
• Shen Dan

Classifications

• H03F3/187

  in integrated circuits · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03F3/005

  using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence) · CPC title

• H03F1/025

  by using a signal derived from the input signal · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title